Specifications

Interrupt Controller (V40)
Next, an IRQ1 request occurs. Since interrupts are automatically
disabled upon entering a service routine, the IRQ1 request is not
acknowledged until the "set interrupt" command is executed. Note
that if a lower priority input such as IRQ4 generates a request, it will
not be serviced until all higher priority requests are serviced. The
CPU vectors program execution to the IRQ1 service routine.
At this point in the sequence, the IIS register has bits IRQ3 and IRQ1
set. This means that IRQ0 is the only input with a high enough
priority to generate a request to the CPU. The IRQ1 service routine is
terminated with the "finish interrupt" command. This command clears
the IRQ1 bit in the IIS register. The "interrupt return" instruction
vectors program execution back to the IRQ3 service routine. At this
point IRQ0 through IRQ2 have high enough priority to generate an
interrupt to the CPU. This routine is again completed with a "finish
interrupt" command and "interrupt return" instruction.
8-24