Specifications

Interrupt Controller (V40)
Interrupt Nesting
Interrupt nesting is a powerful structure that allows an interrupt
currently under service to be suspended while a second interrupt is
serviced. The ICU supports nested interrupts. In most cases, the
second interrupt must be a higher priority than the one currently being
serviced. The exceptions to the rule are listed below.
• Any ICU using the Self Finish mode
• Any ICU using the Exceptional Nesting mode
The best way to understand nested interrupts is to examine the
operation of the Interrupt Request (IRQ) and Interrupt In-Service (IIS)
registers when multiple interrupt requests are generated. A bit in the
IRQ register is set when an interrupt request is generated. More than
one bit of the IRQ register will be set if more than one request occurs
between interrupt acknowledge cycles. During the interrupt
acknowledge cycle, the highest priority request is selected from the
IRQ register and the vector for that request sent to the CPU. The
corresponding bit of the IIS register is also set to flag that the request
is currently being serviced. This bit remains set until a finish interrupt
command is sent to the ICU.
In nested operation, further requests of the same or lower priority are
inhibited while the IIS bit is set. A higher priority request can still
interrupt the CPU and vector program operation to its own service
routine if the "set interrupt" command is executed in the service
routine of the device currently being serviced.
An example of nested interrupt execution is illustrated in Figure 8-13.
This example assumes that the interrupt request inputs are prioritized
with IRQ0 having the highest priority and IRQ7 having the lowest.
The example begins in the main program. The "set interrupt"
command must be executed before an interrupt is recognized after
power on or reset. The CPU vectors program execution to the IRQ3
service routine in response to the IRQ3 request.
8-22