Specifications

Interrupt Controller (V40)
The V40 interrupt acknowledge cycle is two machine cycles long and
looks much the same as two I/O read cycles. The difference is that the
CPU interrupt acknowledge signal is pulsed low for two clock periods
each machine cycle instead of the read signal. The first interrupt
acknowledge pulse prepares the ICU to provide an interrupt vector on
the second. Preparation includes freezing the state of the interrupts
internal to the ICU so the highest priority request can be determined.
The ICU supplies an interrupt vector onto the CPU data bus in
response to the second interrupt acknowledge pulse.
The interrupt vector is an 8-bit value used to point the CPU to an
interrupt service routine for the peripheral device being
acknowledged. A unique vector is generated by the ICU for each
interrupt request input. The CPU reads the vector from the data bus
and multiplies it by four to point to the address of the service routine.
The CPU then begins executing the interrupt service routine at this
address. See the following section, entitled "Interrupt Vectors," for
more information on the interrupt vector and how it relates to the
address of the service routine. The CPU automatically disables
interrupts at the start of the interrupt service routine and does not
enable them again until the interrupt service routine is completed.
This means the CPU will not acknowledge interrupt requests of a
higher priority from the ICU until it is finished servicing the current
request. The "clear interrupt" instruction can be used to enable
interrupts before completion of the current service routine.
The "return from interrupt" is the last instruction of the interrupt
service routine. This instruction enables interrupts and transfers
program execution back to the interrupted program by restoring the
Instruction Pointer, Program Segment, and Processor Status Word
from the stack.
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