Specifications

Interrupt Controller (V40)
OPERATION
Reset
The ICU registers are not initialized to a default state when power is
applied to the ZT 8832 or after a reset. The OPCN V40 configuration
register is initialized to disable the ICU, which disables interrupts.
Interrupts
Most microprocessor systems include peripheral devices designed to
perform specific tasks. Examples include counter/timers, serial
controllers, and real-time clocks. The CPU has the job of managing
the peripherals to meet the needs of specific applications. One method
of peripheral management is for the CPU to start them on a job and
periodically poll for completion. The problem with this method is that
the overhead associated with polling reduces system throughput. As
the number of peripheral devices increases, so does the amount of
time spent polling. Interrupts provide the peripheral device with a
method of informing the CPU when it is ready to be serviced. The
following discussion explains how interrupting peripherals are
serviced in a V40-based system.
A peripheral device needing service generates an interrupt request on
one of the inputs to the ICU. The ICU responds by interrupting the
CPU if the incoming interrupt is not masked and has the highest
priority. Interrupt masking and priorities are explained later in this
section. Interrupts must be enabled in the CPU before the CPU can
recognize the interrupt request from the ICU. The CPU interrupts are
disabled after reset and must be enabled using the "set interrupt"
instruction. The CPU recognizes interrupts by storing the current
program location (Instruction Pointer and Program Segment) and
status (Processor Status Word) on the stack and entering an interrupt
acknowledge cycle. The current program location and status are
preserved on the stack as a return pointer that allows program
execution to continue after the interrupt is serviced.
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