Specifications

Interrupt Controller (V40)

Figure 8-11 shows the IPOL status word. Bits PL0 through PL2

define the highest priority interrupt input requesting service. For

example, if all three bits are set to a logical 1, then IRQ7 is the

highest priority request.

The INT bit (bit 7) indicates whether there are any interrupt

requests. A logical 1 signals an interrupt request and a logical 0

signals no interrupt request. If INT is a logical 0, PL0 through

PL2 are all set to a logical 1. The typical polling sequence is to

set the POL bit in IMDW, read the IPOL register, and test the

INT bit. If INT is a logical 1, decode PL0 through PL2 to

determine which peripheral to service.

Address:Base + 0

Access:Read

76543210

PL2 PL1 PL0

Highest Active Request

000 IRQ0

001 IRQ1

010 IRQ2

011 IRQ3

100 IRQ4

101 IRQ5

110 IRQ6

111 IRQ7

0000INT

Interrupt

0 No interrupt present

1 Interrupt present

Figure 8–11. Interrupt Status Register IPOL.

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