Specifications

Interrupt Controller (V40)
The IL0 through IL2 bits designate an interrupt level. This level
is used by certain combinations of the FI, SIL, and RP bits either
to reset an interrupt request that has been recognized or to set a
specific priority.
The ICU uses the IIS register to keep track of which interrupts are
being serviced and their relative priorities. The ICU updates the
IIS register based on a Finish Interrupt command. There are three
methods of generating the finish interrupt command: specific FI,
nonspecific FI, and automatic FI. The automatic FI is
programmed with IIW4. The specific and nonspecific FI are
selected with the FI bit. A logical 1 in FI enables the specific or
nonspecific FI, based on the SIL and RP bits.
The SIL bit enables bits IL0 through IL2 for selected operations.
IL0 through IL2 indicate an interrupt level to be reset during the
finish interrupt commands or a new priority for priority rotation
commands.
The ICU provides several methods of establishing priorities for
the interrupt request inputs. The RP bit selects the priority
rotation options. A logical 1 in the RP bit indicates that rotation in
priorities is to take place based on the values of the FI and SIL
bits. A logical 0 in the RP bit means that no priority rotation will
take place.
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