Specifications

Interrupt Controller (V40)
Operation Words (IMKW, IPFW, and IMDW)
Once initialized, the operation of the ICU is controlled with three
8-bit values called the Interrupt Mask Word (IMKW), Interrupt
Priority and Finish Word (IPFW), and the Interrupt Mode Word
(IMDW). The Operation Words can be transferred in any sequence to
perform such functions as enabling and disabling individual interrupt
requests and changing interrupt priorities.
IMKW
The IMKW masks interrupt request inputs. Interrupts are masked
by writing IMKW to the IMK register. IMKW can be read
directly from the IMK register to determine the current status of
the mask. This eliminates the need for application software to
maintain a copy of the mask in program memory.
As shown in Figure 8-7, each of the eight bits in IMKW repre-
sents an interrupt input. Bit M0 is used to mask IRQ0, M1 is used
to mask IRQ1, and so on. Setting a bit in IMKW to a logical 1
prevents the interrupt request for the respective input from being
acknowledged by the ICU. The interrupt request is latched in the
IRQ register but it never reaches the IIS register.
IMKW
Address: Base + 1
Access: Read/Write
76543210
M7 M6 M5 M4 M3 M2 M1 M0
Interrupt Request Mask
Each bit:
0 IRQn not masked
1 IRQn masked
Figure 8–7. Interrupt Mask Word.
8-12