Specifications

Interrupt Controller (V40)
The ICU responds to an interrupt acknowledge by supplying the
CPU with an interrupt vector based on which interrupt generated
the request and the value programmed into IIW2. The format for
IIW2 is shown in Figure 8-4. Bits V3 through V7 define the upper
5 bits of the vector address.
IIW2
Address: Base + 1
Access: Write
76543210
V7 V6 V5 V4 V3
Higher 5 bits of
interrupt vector number
Figure 8–4. Interrupt Initialization Word 2.
IIW3
The ZT 8832 does not support cascading the interrupt controller
inputs to other interrupt controllers. Bits 0 through 7 must be pro-
grammed with logical 0s, as shown in Figure 8-5.
IIW3
Address: Base + 1
Access: Write
76543210
00000000
Figure 8–5. Interrupt Initialization Word 3.
8-10