Specifications

Interrupt Controller (V40)
Interrupt Mask Register
All interrupt requests are latched by the Interrupt Request register.
The Interrupt Mask register acts as a programmable filter to
selectively disable requesting interrupts from being serviced. The
IMK is an 8-bit register with one bit position for each interrupt input.
Setting a bit to a logical 1 prevents the respective interrupt request
from being transferred from the Interrupt Request register to the
Interrupt In-Service register.
Priority
Resolver
All interrupt requests are latched into the Interrupt Request register.
Those not masked by the Interrupt Mask register are input to the
Priority Resolver to determine which is to be serviced. The interrupt
request with the highest priority is transferred from the Interrupt
Request register to the Interrupt In-Service register during the
interrupt acknowledge cycle. The ICU includes several programmable
operating modes that define the rules by which the Priority Resolver
determines the highest priority interrupt request. These modes range
from all inputs having equal priority to rotating the priorities each
time an interrupt is serviced.
Interrupt In-Service
Register
The 8-bit Interrupt In-Service register maintains a bit position for each
interrupt request that is currently being serviced. More than one bit
can be set if an interrupt is currently under service and a second
interrupt request is acknowledged. The IIS register is read to
determine the status of the interrupts currently being serviced. A
logical 1 in a bit position means that the interrupt is currently being
serviced.
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