Specifications

Counter/Timers
Multiple Latch Mode
Programming the Select Counter bits of the TMD to logical 1s
defines the Multiple Latch command (see Figure 7-4). The
CNT0, CNT1, and CNT2 bits select which of the counter/timers
will be latched. The Status Latch and Count Latch bits determine
whether the status, the count, or both are to be latched. The status
must be latched to be read. The count can be read without being
latched, but will be invalid if it is changing at the time of the read.
Register: Timer Mode (TMD)
Address:Base + 3
76543210
0
CNT0
Counter/Timer 0 Select
0 CNT0 not selected
1 CNT0 selected
CNT1
Counter/Timer 1 Select
0 CNT1 not selected
1 CNT1 selected
CNT2
Counter/Timer 2 Select
0 CNT2 not selected
1 CNT2 selected
SL
Status Latch
0 Latched
1 Not latched
CL
Count Latch
0 Latched
1 Not latched
11
Figure 7–4. Counter/Timer Multiple Mode Register.
7-11