Specifications

Counter/Timers
Timer Mode Register (TMD)
The counter/timers must be initialized with the 8-bit TMD register.
The three formats for the TMD register are shown in Figures 7-2, 7-3,
and 7-4 (pages 7-9 to 7-11). The General Mode format is pro-
grammed initially to define the operation of the counter/timers. The
Count Latch Mode and Multiple Latch Mode are programmed at any
time to read the count and status data while the counter/timers are
operating.
General Mode
The General Mode format, shown in Figure 7-2, specifies the
operating mode of the individual counter/timers. The Select
Counter bits specify the Multiple Latch command, or which
counter/timer will receive the mode. Selecting the Multiple Latch
command changes the definition of the TMD register bits to that
of the Multiple Latch Mode format. The following bit definitions
apply only if the Multiple Latch and Count Latch options are not
programmed.
The Read/Write Mode bits specify the Count Latch command, or
the format of the count transferred between the CPU and the
TCU. Selecting the Count Latch command redefines the bits of
the TMD register to that of the Count Latch Mode format.
The count transferred to or from the 16-bit counter/timers is one
or two 8-bit values, depending on the Read/Write Mode bits. If
the low byte option is chosen, the 8-bit count transferred to the
counter/timer is placed into the low byte of the Down Counter
and the high byte is automatically set to zero. The high byte
option means that the 8-bit count is transferred to the upper byte
of the Down Counter with the low byte set to zero. Selecting the
two-byte option prepares the counter/timer to receive two bytes,
placing the first into the lower byte of the Down Counter and the
second into the upper.
7-8