Specifications

Counter/Timers
The Count register and Count Latch are the interface through which
the count data is transferred between the TCU and the CPU. The
Count register receives the count value programmed to the TCU. The
count value can be either 8 bits or 16 bits. Eight-bit values can be
specified as either upper or lower bytes.
A useful feature of counter/timers is that they can be read at any time.
It may be necessary to read a counter while an application is operating
to determine how much time remains in a timing loop, or how many
external events have occurred. The contents of the Down Counter,
however, can change during the read operation, producing undefined
results.
While one solution is to stop the Down Counter, this causes
inaccuracies in the overall timing loop, or may cause an external event
to be missed. The TCU solves this problem with the Count Latch and
with commands that freeze the contents of the Count Latch without
affecting the Down Counter. The Count Latch normally holds the
current value of the Down Counter. When the TCU receives a count
latch command, the Count Latch stops changing long enough for the
read operation to occur, then returns to tracking the contents of the
Down Counter.
The Status register contains information about the counter/timer’s
operation, such as the programmed operating mode. This eliminates
the need for application software to store this information. The Status
Latch allows the status to be read during times when status bits may
be changing.
The Control Logic manipulates other functional blocks of the
counter/timer, depending on which of the six programmable operating
modes is selected, the state of the clock (TCLK), and, for
counter/timer 2 only, the control input (TCTL2).
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