Specifications

Counter/Timers
ZT 8832 SPECIFICS
The clock source for each counter/timer is defined in the TCKS V40
configuration register. Choices for the clock source are either the V40
internal clock or the TCLK signal. The clock internal to the V40 has a
frequency of 8 MHz and a duty cycle of 50%. The TCLK signal is
available through connector J3. The TCLK signal must meet the
following requirements:
• Operating frequency between DC and 8 MHz
• Rise and fall times less than 25 ns
• Clock low and clock high times greater than 50 ns
Counter/timers 0 and 1 have implied uses because of their dedicated
output connections to other devices internal to the V40. The output of
counter/timer 0 is connected to IRQ0 of the interrupt controller. This
dedicates counter/timer 0 to generating timed or periodic interrupts.
The output of counter/timer 1 is connected to the V40 serial port for
baud rate generation. The output of counter/timer 1 can also be
connected to IRQ2 of the interrupt controller if the V40 serial port is
not needed. This connection is made with the OPCN V40
configuration register.
Counter/timer 2 does not have an implied use. The output (TOUT2)
and control (TCTL2) signals for counter/timer 2 are available through
connector J3, to be used as required by the application.
7-3