Specifications

Processor Configuration (V40)

The CS0, CS1, and CS2 (Clock Select 0, 1, and 2) bits select the

counter/timer clock source to be either the reference clock internal to

the V40 or the TCLK pin available on an external V40 pin. The V40

clock operates at 8 MHz with a 50% duty cycle. The TCLK signal is

available through connector J3. The Prescale (PS) field selects a

prescale value that divides the clock frequency of all counter/timers

using the V40 internal clock, then applies that value to the

counter/timers. The STD ROM software programs all bits of TCKS

with logical 0s to configure counter/timer 1 for baud rate generation.

Address:FFF0h

76543210

Prescale Select for Internal Clock

00 Clock prescaled by 2

01 Clock prescaled by 4

10 Clock prescaled by 8

11 Clock prescaled by 16

CS0

Counter/Timer 0 Clock Source

0 Internal clock

1 TCLK pin

CS1

Counter/Timer 1 Clock Source

0 Internal clock

1 TCLK pin

CS2

Counter/Timer 2 Clock Source

0 Internal clock

1 TCLK pin

———

Figure 6–7. Timer/Counter Clock Selection Register.

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