Specifications

Processor Configuration (V40)

The Middle Memory Block is defined between the top of the LMB

and the bottom of the UMB. Offboard memory (STD bus) requires

one wait state in all cases and is defined by the MMB.

The LMB field defines the lower memory address range starting from

zero. This field can be programmed to include the memory devices

inserted into the RAM LOW and RAM HIGH sockets. The UMB

field defines the upper memory address range ending at FFFFFh. This

field can be programmed to include the memory device inserted into

the ROM socket. The STD ROM software initializes all bits of the

WMB register to logical 0s.

RFC - Refresh Control

The refresh controller is not used by the ZT 8832. To prevent the

refresh controller from affecting system performance, program bit 7

with a logical 0 (see Figure 6-6).

Address:FFF2h

76543210

———————0

Figure 6–6. Refresh Control Register.

TCKS - Counter/Timer Clock Selection

The V40 includes three programmable counter/timers. The TCKS

counter/timer, and also selects a frequency divisor that is used by all

three counter/timers.

6-10