Specifications

Processor Configuration (V40)
WMB - Wait Memory Boundary Register
The ZT 8832 does not require any wait memory wait states if memory
devices with access times less than 250 ns are used. If slower memory
devices are used, the WMB register divides the ZT 8832 memory into
three regions and the WCY1 register defines the number of wait states
inserted into each. As shown in Figure 6-5, the WMB register is
divided into Upper Memory Boundary (UMB) and Lower Memory
Boundary (LMB) fields.
Register:WMB
Address:FFF4h
76543210
UMB
Upper Memory Block Size
000 32 Kbytes
001 64 Kbytes
010 96 Kbytes
011 128 Kbytes
100 192 Kbytes
101 256 Kbytes
110 384 Kbytes
111 512 Kbytes
—LMB
Lower Memory Block Size
000 32 Kbytes
001 64 Kbytes
010 96 Kbytes
011 128 Kbytes
100 192 Kbytes
101 256 Kbytes
110 384 Kbytes
111 512 Kbytes
—
FFFFFh
00000h
Higher Memory Block (UMB)
Middle Memory Block (MMB)†
Lower Memory Block (LMB)
† MMB is defined as the address range between
LMB and UMB.
Figure 6–5. Wait-Cycle Memory Boundary Register.
6-9