Specifications

Processor Configuration (V40)
The ZT 8832 does not require any memory wait states if memory
devices with access times less than 250 ns are used. To select zero
memory wait states, program bits 0 through 5 with logical 0s.
Programming bit 6 with a logical 0 and bit 7 with a logical 1 selects
the two I/O wait states required by peripherals on the ZT 8832. The
STD ROM software programs the WCY1 register with an 80h.
Register:WCY1
Address:FFF5h
76543210
LMW
Lower Memory Region
00 0 wait states
01 1 wait state
10 2 wait states
11 3 wait states
MMW
Middle Memory Region (STD Bus)
00 0 wait states
01 1 wait state
10 2 wait states
11 3 wait states
UMW
Upper Memory Region
00 0 wait states
01 1 wait state
10 2 wait states
11 3 wait states
01
Figure 6–4. Wait-Cycle 1 Register.
6-8