Specifications

Processor Configuration (V40)

WCY2 - Wait Cycle 2 Register

The V40 includes a programmable wait-state generator that interfaces

to memory and I/O devices that are not fast enough to operate without

wait states. The wait-state generator is programmed through the

WCY2, WCY1, and WMB configuration registers. The format of the

WCY2 register is shown in Figure 6-3. Bit 2 must be programmed

with a logical 0 and bit 3 must be programmed with a logical 1 to

select two wait states into DMA cycles. Two wait states are required

to meet the SBX expansion module timing requirements. The STD

ROM software initializes the WCY2 register with a 08h.

Address:FFF6h

76543210

——01————

Figure 6–3. Wait-Cycle 2 Register.

WCY1 - Wait Cycle 1

The WCY1 register is divided into four fields as shown in Figure 6-4

on page 6-8. The first three fields define the number of wait states

inserted into three different regions of memory defined by the WMB

of wait states inserted for memory accesses into the low memory

region. The Middle Memory Wait (MMW) field defines the number

of wait states inserted for memory accesses into the middle memory

region. The Upper Memory Wait (UMW) field defines the number of

wait states inserted for memory accesses into the upper memory

region.

6-7