Specifications

Processor Configuration (V40)
OPHA, DULA, IULA, TULA, and SULA
Five registers determine the I/O base address of the programmable
registers used to communicate with the DMA controller, interrupt
controller, timer/counters, and serial controller.
OPHA - On Chip Peripheral High Address register (FFFCh)
DULA - DMA Unit Low Address register (FFFBh)
IULA - Interrupt Unit Low Address register (FFFAh)
TULA - Counter/timer Unit Low Address register (FFF9h)
SULA - Serial Unit Low Address register (FFF8h)
The I/O base address is a 16-bit value made up of two 8-bit values.
The upper 8 bits of the address for the DMA controller, interrupt
controller, counter/timers, and serial controller are defined by the
OPHA register. The lower 8 bits for the DMA channel are
programmed in the DULA register. The same holds true for the
interrupt controller and IULA register, for the counter/timers and
TULA register, and for the serial controller and SULA register.
In operation, OPHA permits the four internal peripheral devices to be
mapped to any 256 byte block in the 64K I/O address space. The
individual registers DULA, IULA, TULA, and SULA are
programmed to define the base address of each of these devices
anywhere within this block. For example, if the interrupt controller is
to be mapped starting at I/O address FF20h, OPHA must be
programmed with a FFh and IULA with a 20h.
6-5