Specifications
Processor Configuration (V40)
OPCN - On Chip Peripheral Connection Register
Figure 6-1 shows the OPCN register. Bit 0 must be programmed with
a logical 0 and bit 1 must be programmed with a logical 1.
The two bits of the IRSW field select the interrupt source to be
assigned to IRQ1 and IRQ2 of the interrupt controller. The values
programmed into bits 2 and 3 depend on the use of the interrupt
controller in the application. The pins external to the V40 used for
IRQ1 and IRQ2 are connected to Stage 1 of the watchdog timer and
Interrupt 0 of the SBX expansion module, respectively. The
STD ROM software initializes OPCN to a 06h to use the V40 serial
port.
Register: OPCN
Address: FFFEh
76543210
01IRSW
Interrupt Request Switch
INT1 INT2
00 IRQ1 pin IRQ2 pin
01 SCU IRQ2 pin
10 IRQ1 pin TOUT1
11 SCU TOUT1
————
Figure 6–1. On Chip Peripheral Connection Register.
6-3