Specifications

Processor Configuration (V40)
VCR - V40 CONFIGURATION REGISTERS
The 12 V40 configuration registers are mapped from I/O address
FFF0h through FFFFh. The registers are listed in Table 6-1 and are
discussed in detail on the following pages. All of the registers can be
written to with the output instruction and read from with the input
instruction. The value input may be different from the value output,
but only in the bits not defined.
Table 6-1
V40 Configuration Registers.
I/O
Address Register Function
FFFFh Reserved --
FFFEh OPCN V40 multiplexed pin assignment
FFFDh OPSEL V40 peripheral enable
FFFCh OPHA V40 peripheral I/O address (MSB)
FFFBh DULA DCU I/O address (LSB)
FFFAh IULA ICU I/O address (LSB)
FFF9h TULA TCU I/O address (LSB)
FFF8h SULA SCU I/O address (LSB)
FFF7h Reserved --
FFF6h WCY2 DCU wait states
FFF5h WCY1 CPU memory and I/O wait states
FFF4h WMB Memory wait state boundaries
FFF3h Reserved --
FFF2h RFC Refresh enable, frequency select
FFF1h Reserved --
FFF0h TCKS Timer/counter clock selection
6-2