Specifications

Processor Description (V40)
A hardware interrupt suspends the 8080 emulation mode. The CPU
pushes the PSW [FL] and return address onto the native mode stack,
sets the MD flag to a logical 1, and transfers program execution to the
native mode interrupt service routine. When the CPU executes the
RETI [IRET] instruction, the PSW [FL] is restored with the MD flag
set to a logical 0, and program execution continues in the emulation
mode. The CALLN instruction permits the execution of native mode
subroutines from emulation mode. The CPU responds to CALLN in
the same manner as a hardware interrupt.
The emulation mode cannot be nested. For example, assume that the
CPU is operating in native mode and executes the BRKEM
instruction. The CPU switches to native mode and begins executing
emulation code. Next, assume that a hardware interrupt (such as the
16450 serial controller) suspends emulation mode and the CPU begins
executing the interrupt service routine in native mode. That interrupt
service routine cannot include a BRKEM instruction.
Table 5-6 on page 5-36 shows the relationship between the native and
emulation mode registers and flags. The native mode registers not
shown are inaccessible to 8080 programs; they are AH [AH], PS
[CS], SS [SS], DS0 [DS], DS1 [ES], IX [SI], IY [DS], and the upper
eight bits of the PSW [FL].
Memory addressing and stack referencing must also be considered.
The 8080 addresses a maximum of 64 Kbytes. This block of memory
can be located anywhere in the 1 Mbyte address space by pro-
gramming the PS [CS] word in the interrupt vector table before the
BRKEM instruction is executed. All data and stack operations are
referenced from the DS0 [DS] register. This register must be
initialized before the BRKEM instruction is executed. The values in
the PS [CS] and DS0 [DS] registers must be equal for complete
compatibility with the 8080 structure.
5-35