Specifications

Processor Description (V40)

Before describing each source of interrupt shown in the vector table, it

is useful to summarize the operation of the CPU in response to an

interrupt. Interrupts come to the CPU from three sources: the NMI

signal external to the V40, the output of the ICU, and from inside to

the CPU itself. A vector is supplied in all cases to distinguish between

the interrupting sources. The CPU determines the address of the

service routine by multiplying the vector times four. Before

transferring execution to the service routine, the CPU saves the

machine status by pushing the current contents of the PSW [FL] and

the return address onto the stack. The CPU then clears the BRK [TF]

and IE [IF] flags to prevent subsequent single-step and maskable

interrupts, and transfers program execution to the service routine. The

service routine is terminated with a "return from interrupt" instruction.

This instruction causes the CPU to restore the PSW [FL] from the

stack and return execution to the interrupted program. Restoring the

PSW [FL] automatically enables single-step and maskable interrupts.

Divide Err

The divide error interrupt is generated by the CPU following

execution of a DIV [DIV] or DIVU [IDIV] instruction if the

calculated quotient is larger than the specified destination. The

interrupt is not maskable and the vector is fixed at zero.

Single-Step

The single-step interrupt is a powerful software debugging tool. The

purpose of the single-step interrupt is for software single stepping

through a sequence of code. This interrupt is controlled by the BRK

[TF] flag in the PSW [FL]. There is no instruction to set the BRK

[TF] flag. To set the BRK [TF] flag, the PSW [FL] register must be

pushed on the stack, the flag set, and the PSW [FL] popped back off

the stack. With the BRK [TF] flag set, a single-step interrupt is

generated after each instruction. The CPU responds to the interrupt by

pushing the PSW [FL], PS [CS], and PFP [IP] on the stack. The BRK

[TF] and IE [IF] are reset to a logical 0 to prevent another single-step

or maskable interrupt. Upon completion of the single-step routine, the

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