Specifications

Processor Description (V40)
INTERRUPTS
The V40 includes a versatile interrupt structure that supports both
hardware and software initiated interrupts. Hardware interrupts are
external inputs to the V40 and can be classified as maskable or non-
maskable. Maskable interrupts are routed to the CPU through the
ICU. The ICU provides the maskable interrupt inputs with the ability
to be level- or edge-triggered, have fixed or rotating priorities, and be
individually masked. Non-maskable interrupts are routed directly to
the CPU and are not maskable through programming.
Software interrupts are internally generated during program
execution. They include instructions that can be executed to generate
interrupts, and error handling instructions for such things as a divide
overflow. Table 5-4 on page 5-28 lists the sources of hardware and
software interrupts. The remainder of this section explains these
interrupts and how the V40 handles them.
5-27