Specifications

Processor Description (V40)
The lower 16 of the 20 address lines are also used to address I/O
devices. With 16 bits of address, the V40 can directly access up to
64 Kbytes of I/O. The address range is from 0 to FFFFh, as shown in
Figure 5-7. Address locations FF00 through FFEFh are reserved for
future use. The address range from FFF0 through FFFFh is currently
used for the V40 configuration registers. These registers define pro-
grammable options in the V40, such as wait-state insertion, location
of internal peripheral device registers, enabling DRAM refresh, and
selecting the period of refresh.
DEDICATED
RESERVED
GENERAL PURPOSE
FFFFh
FFF0h
FFEFh
FF00h
FEFFh
0000h
Figure 5–7. I/O Map.
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