Specifications

Processor Description (V40)
MEMORY AND I/O ADDRESSING
This section discusses how the V40 communicates with memory and
I/O devices. The V40 has a 20-bit address bus and an 8-bit data bus.
With 20 bits of address, the V40 can directly access up to 1 Mbyte of
memory. The address range is from 0 to FFFFFh, as shown in
Figure 5-5. Address locations 0 to 7Fh are reserved for dedicated
interrupts and future enhancements. The address range from 80 to
3FFh completes the interrupt vector table and may be used as needed
by the application. The 12 bytes (six words) from FFFF0 to FFFFBh
are the area vectored to by the V40 after a reset. The most common
practice is to program this area with an intersegment jump to the start
of the application program. The upper four bytes are reserved and
must not be programmed.
RESERVED
RESET VECTOR
GENERAL PURPOSE
INTERRUPTS
FFFFFh
FFFFCh
FFFF0h
FFFEFh
FFFFBh
00400h
003FFh
00000h
Figure 5–5. Memory Map.
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