Specifications

Processor Description (V40)
the buses at any given time. The bus masters are prioritized in the
following order:
(1st) DCU - DMA Control Unit
(2nd) HLDRQ - External Bus Master
(3rd) CPU - Central Processing Unit
If the bus is being used by one bus master and another with higher
priority makes a request, the BAU inactivates the current bus master’s
acknowledge. The BAU grants access to the higher priority bus
master after the current bus master removes the request.
The BUSLOCK prefix prevents all bus masters, other than the CPU,
from gaining access to the bus. Care must be taken to prevent loss of
data in dynamic RAM when using the BUSLOCK prefix with
instructions that have a long execution time.
CGU - Clock Generator
Unit
The CGU halves the frequency of the external oscillator to provide a
clock reference with a 50% duty cycle to the CPU. This same signal
is available on an external pin called CLKOUT to which all of the
V40 timing parameters are referenced.
VCR - V40 Configuration
Registers
Twelve programmable registers are used to configure the V40 to meet
the needs of varying applications. The V40 configuration registers are
located in the top 16 bytes of the 64 Kbytes of I/O address space. The
configuration registers define the functions of the programmable pins;
the enabling and disabling of the SCU, TCU, ICU, and DCU; the
location of the SCU, TCU, ICU, and DCU programmable registers in
I/O address space; the wait-state configuration; DRAM refresh; and
the counter/timer clock source.
5-20