Specifications

Processor Description (V40)
BIU - Bus Interface Unit
The BIU controls the external address, data, and control buses. The
BIU also synchronizes the RESET and READY inputs with the clock,
as shown in Figure 5-4. The synchronized RESET signal is used
internally. It is provided externally as a signal called RESOUT. The
synchronized READY signal is combined with the output of the Wait
Control Unit to control the number of wait states inserted during bus
operations.
RESOUT
To Internal Circuit
To Internal Circuit
CK
QD
CK
Q
D
D
Q
CK
READY
RESET
CLOCK
Figure 5–4. RESET and READY Synchronization.
BAU - Bus Arbitration
Unit
The V40 includes two internal bus masters and two signals supporting
one external bus master. The two internal bus masters are the Central
Processing Unit and DMA Control Unit. An external master, such as
the 8087 numeric data processor, is supported with the HLDRQ and
HLDAK signals. Each of the three bus masters mentioned above
needs access to the address, data, and control buses to perform its
function. The BAU controls which of these bus masters has access to
5-19