Specifications

Processor Description (V40)
the array during a string operation. After a string operation is
completed, the index registers are incremented or decremented,
depending on the state of the DIR [DF] flag. If the DIR [DF] flag
is set, the index is incremented to point to the next array element.
If the DIR [DF] flag is reset, the index is decremented.
IE [IF] (Interrupt Enable Flag) - The IE [IF] flag determines
how the CPU responds to maskable external interrupts. If IE [IF]
is set, the CPU recognizes maskable external interrupts. The CPU
ignores all maskable external interrupts if IE is reset. IE [IF] has
no effect on external non-maskable interrupts or on internally
generated interrupts. IE [IF] is set or reset with dedicated
instructions, but will also be reset automatically with a return
from interrupt instruction.
BRK [TF] (Break Flag) - Setting the break (or trap) flag puts the
CPU into a single-step operation useful for testing program
execution. With BRK [TF] set, the CPU automatically generates
an internal interrupt after each instruction. The programmer need
only develop an interrupt service routine to examine contents of
registers, dump memory, or do whatever is necessary for testing.
The BRK [TF] flag is set or reset by transferring the PSW [FL] to
the program stack and using memory manipulation instructions to
modify it. Once BRK [TF] is modified, it must be transferred
back to the PSW [FL] to generate a type 1 interrupt after the
execution of each instruction. As part of the interrupt
acknowledge, the PSW [FL] is saved on the stack and the BRK
[TF] flag is reset. This is done so that the processor will not
single-step through the interrupt service routine. Once the service
routine is completed, the PSW [FL] is restored from the stack
automatically, setting the BRK [TF] flag to trap the next
instruction.
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