Specifications

Processor Description (V40)
12 clocks to calculate the effective address using microcode.
However, the V40 does all effective address calculations in two
clocks with the hardware EAG.
The effective address, once calculated by the EAG, is transferred
to the DP register, where it can be used by the BCU to transfer
data between the CPU and memory.
Program Status Word
PSW [FL]
There are six status flags and four control flags in the 16-bit PSW
[FL], as seen in Figure 5-3. Notice that not all 16 bits are defined.
Those not defined are reserved; that is, they may be used in later
versions of the processor. Because of this, a program should never
rely on a value in any of these reserved bits.
STATUS FLAGS:
Carry
Parity
Auxiliary Carry
Zero
Sign
Overflow
CONTROL FLAGS:
Break
Interrupt Enable
Direction
Mode
STATUS
WORD:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD
V
[OF]
DIR
[DF]
IE
[IF]
BRK
[TF]
S
[SF]
Z
[ZF]
AC
[AF]
P
[PF]
CY
[CF]
Figure 5–3. Processor Status Word.
The status flags provide information about the result of arithmetic
and logic operations. The status flags are set (logical 1) and reset
(logical 0) by the EXU based on the result of an arithmetic or
logic operation. These flags can be tested by conditional jump
instructions to change the order of program execution.
5-14