Specifications

Processor Description (V40)
For sequentially addressed instructions, the PFP [IP] is incremen-
ted by the number of bytes of the current instruction to point to
the next. For program branching, such as intrasegment and
intersegment jumps, the PFP [IP] is programmed with a value
contained within the jump instruction. The PFP [IP] is not
accessible to the programmer.
Data Pointer
DP
This 16-bit register is the destination for the offset address
calculated by the effective address generator. The offset address
calculation is done by hardware instead of the traditional
microcode, saving three to ten clock cycles for every calculation.
The DP register is not accessible to the programmer.
Instruction Queue
Q0 - Q3
The instruction queue is a temporary storage location for program
instructions and variables that have been fetched by the BCU to
be executed by the EXU. The instruction queue consists of four
8-bit registers, Q0 through Q3. These registers allow instruction
fetching by the BCU and instruction execution by the EXU to be
independent operations. This overlap essentially eliminates the
time required to fetch program instructions and data. Q0 through
Q3 are not accessible to the programmer.
Address Modifier
ADM
The V40 uses a 20-bit memory address to access any location in
the 1 Mbyte addressing range. The 20-bit memory address is the
sum of a segment (shifted left four bits) and an offset. The offset
is taken from the PFP [IP] if a program instruction is being
addressed or from the DP for all other data. The ADM does this
addition. If the PFP [IP] was used, the ADM increments it for the
next instruction. The ADM is not accessible to the programmer.
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