Specifications

Processor Description (V40)
CPU Functional Blocks
The functional blocks in Figure 5-2 are described below. The NEC
mnemonic is shown for each block, followed by the Intel mnemonic
in brackets. For example, the CPU flag register is represented by
PSW [FL] because NEC labels it Processor Status Word and Intel
labels it Flags.
Segment Registers
PS [CS], SS [SS], DS0 [DS], and DS1 [ES]
The CPU can address up to 1 Mbyte of memory in segments of
64 Kbytes or less. The starting address of a segment is specified
in a segment register. The four segment registers are as follows:
PS [CS] - Program Segment register
SS [SS] - Stack Segment register
DS0 [DS] - Data Segment register 0
DS1 [ES] - Data Segment register 1
All memory addresses are specified with a segment and offset as
shown in Table 5-1. The segment and offset used depend on the
type of instruction being executed.
The program always resides in a program segment pointed to by
the PS [CS] register. The PFP [IP] always contains the offset
within the program segment. The program stack always resides in
the stack segment pointed to by the SS [SS] register. The SP [SP]
contains the offset of the top of the stack. Stack variables can be
addressed using the BP [BP] register because the default segment
register is SS [SS].
Program variables generally reside in the data segment with the
segment address in the DS0 [DS] register. The offset of the
variable within DS0 [DS] is called the effective address. The
EXU calculates the effective address by summing any
combination of displacement, base register, and index register.
The possible combinations of offset, base, and index provide the
programmer with a large variety of addressing modes.
5-8