Processor Description (V40)
TA, TB, AND TC
ALU
PSW [FL]
Effective Address
Generator
PS [CS]
SS [SS]
DS0 [DS]
DS1 [ES]
PFP [IP]
DP
Q0-Q3
AW [AX]
BW[BX]
CW [CX]
DW [DX]
SP [SP]
BP [BP]
IX [SI]
IY [DI]
PC
LC
ADM
Internal address/data bus (20)
TO BIU
BCU
EXU
Subdata bus (16) Main data bus (16)
Figure 5–2. CPU Block Diagram.
5-7
