ZT 8832 I/O Control Processor OPERATING MANUAL For ZT 8832 Revision 0.5 and ZT 88CT32 Revision 0.
ZIATECH 5+5 WARRANTY For Ziatech Board- and System-Level Computer Products FIVE-YEAR LIMITED WARRANTY Products manufactured by Ziatech Corporation are covered from the date of purchase by a five-year warranty against defects in materials, workmanship, and published specifications applicable to the date of manufacture. During the warranty period, Ziatech will repair or replace, solely at its option, defective units provided they are returned at customer expense to an authorized Ziatech repair facility.
SPECIAL EXTENDED WARRANTY OPTION In addition to the standard five-year warranty, Ziatech offers, for a nominal fee, an extended period of warranty up to five extra years. This extended warranty period provides similar coverage and conditions as stated above in the five-year limited warranty agreement. LIFE SUPPORT POLICY Ziatech products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Ziatech Corporation.
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PREFACE This manual describes the operation and use of the ZT 8832 and the ZT 88CT32. The boards are functionally identical. However, the ZT 88CT32 consumes less power and operates over a wider temperature range. Refer to Appendix B for actual specifications. The term ZT 8832 is used throughout the manual to reference both products, except where otherwise noted. The following organizational outline describes the focus of each chapter in this manual.
Preface III. USER’S REFERENCE Chapter 3, "Theory Of Operation," presents a detailed description of ZT 8832 system level operation. Topics discussed include commonly asked questions, memory and I/O organization, and interrupt structure. Chapter 4, "Application Examples," gives specific examples of the ZT 8832 in operation, including code to implement these applications. Chapter 5, "Processor Description (V40)," divides the V40 into functional blocks and presents a theory of operation for each.
Preface Chapter 9, "DMA Controller (V40)," describes the function, configuration, and operation of the V40 Direct Memory Access Control Unit, a programmable peripheral device used to direct high speed data transfers between the ZT 8832 and SBX expansion module I/O. The chapter also includes register descriptions.
Preface Chapter 15, "Numeric Data Processor (8087)," explains installation and operation of the optional 8087 Numeric Data Processor, used to enhance the math capabilities of the ZT 8832 for numerically intensive applications. IV. APPENDICES Appendix A, "Jumper Selections," provides a detailed explanation of the ZT 8832 options that are selectable through jumper configuration or the use of cuttable traces.
CONTENTS I. INTRODUCTION Chapter 1. INTRODUCTION 1-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Product Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Features of the ZT 8832 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Development Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 FUNCTIONAL BLOCKS .
Contents ZT 88CT32 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 INSTALLING THE ZT 8832 WITH STD ROM . . . . . . . . . . . . . . . . . . . . . 2-5 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Cable Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Jumper Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Program Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Chapter 5. PROCESSOR DESCRIPTION (V40) 5-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents TCKS - Counter/Timer Clock Selection Register . . . . . . . . . . . . . . . . 6-10 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Chapter 7. COUNTER/TIMERS (V40) 7-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 FUNCTIONAL DESCRIPTION . .
Contents Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level- or Edge-Triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finish Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Priority Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specific Priority Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Serial Status Register (SST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Serial Command Register (SCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Serial Mode Register (SMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Serial Interrupt Mask Register (SIMK) . . . . . . . . . . . . . . . . . . . . . . . 10-10 OPERATION . . . . . . . . .
Contents Chapter 12. PARALLEL I/O OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer . . . . . . . . . . . . . . . . . . . . . .
Contents Further Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 IV. APPENDICES Appendix A. JUMPER CONFIGURATIONS A-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 JUMPER OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 CUTTABLE TRACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents V. INDEX Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TABLES Table 2–1 Table 2–2 Table 3–1 Table 5–1 Table 5–2 Table 5–3 Table 5–4 Table 5–5 Table 5–6 Table 6–1 Table 6–2 Table 6–3 Table 7–1 Table 8–1 Table 8–2 Table 9–1 Table 9–2 Table 10–1 Table 10–2 Table 10–3 Table 11–1 Table 11–2 Table 11–3 Table 11–4 Table 11–5 Table 12–1 Table 13–1 Table A–1 Table A–2 Table A–3 Table A–4 Table B–1 Table B–2 STD ROM Jumper Configuration. . . . . . . . . . . . . . . . . . . . . . 2-6 DOS MPX Jumper Configuration. . . . . . . . . . . . . . . . . . . . . .
Tables Table B–3 Table B–4 Table B–5 Table B–6 Table B–7 Table B–8 J1 Parallel Port Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J2 Serial Port (RS-232-C) Pinout. . . . . . . . . . . . . . . . . . . . . J2 Serial Port (RS-422/485) Pinout. . . . . . . . . . . . . . . . . . . J3 Counter/Timer and Interrupt Pinout. . . . . . . . . . . . . . . . J4 SBX Expansion Module Pinout. . . . . . . . . . . . . . . . . . . . J5 Serial Port Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . .
ILLUSTRATIONS Figure 1–1 Figure 2–1 Figure 2–2 Figure 2–3 Figure 2–4 Figure 2–5 Figure 2–6 Figure 3–1 Figure 3–2 Figure 3–3 Figure 3–4 Figure 5–1 Figure 5–2 Figure 5–3 Figure 5–4 Figure 5–5 Figure 5–6 Figure 5–7 Figure 5–8 Figure 6–1 Figure 6–2 Figure 6–3 Figure 6–4 Figure 6–5 Figure 6–6 Figure 6–7 Figure 7–1 Figure 7–2 Figure 7–3 Figure 7–4 Figure 7–5 Figure 7–6 Figure 7–7 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 STD ROM Jumper Configuration. . . . . . . . . . .
Illustrations Figure 7–8 Figure 7–9 Figure 7–10 Figure 7–11 Figure 7–12 Figure 8–1 Figure 8–2 Figure 8–3 Figure 8–4 Figure 8–5 Figure 8–6 Figure 8–7 Figure 8–8 Figure 8–9 Figure 8–10 Figure 8–11 Figure 8–12 Figure 8–13 Figure 9–1 Figure 9–2 Figure 9–3 Figure 9–4 Figure 9–5 Figure 9–6 Figure 9–7 Figure 9–8 Figure 9–9 Figure 10–1 Figure 10–2 Figure 10–3 Figure 10–4 Figure 10–5 Figure 10–6 Figure 11–1 Figure 11–2 Figure 11–3 Figure 11–4 Figure 11–5 Figure 11–6 Figure 11–7 Figure 11–8 Mode 1 Operation. . . .
Illustrations Figure 11–9 Figure 12–1 Figure 13–1 Figure 14–1 Figure 15–1 Figure A–1 Figure A–2 Figure A–3 Figure A–4 Figure B–1 Figure B–2 Figure B–3 Figure B–4 Figure B–5 Figure B–6 Figure B–7 Figure B–8 Figure B–9 Figure B–10 Figure B–11 Figure B–12 Figure B–13 Figure B–14 Figure B–15 ACC Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Parallel Port Functional Diagram. . . . . . . . . . . . . . . . . . . . . 12-3 Watchdog Timer Functional Diagram. . . . . . . . . . . . . .
Chapter 1 INTRODUCTION Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Product Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Features of the ZT 8832 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Development Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 FUNCTIONAL BLOCKS . . . . . . . .
Introduction OVERVIEW This chapter provides a brief introduction to the ZT 8832. It includes a product definition, a list of product features, a functional block diagram, and a description of each block. Unpacking information and installation instructions can be found in Chapter 2, "Getting Started." Product Definition The ZT 8832 is an 8MHz V40-based single board computer designed to operate by itself or as an I/O control processor in an STD bus system.
Introduction Features of the ZT 8832 • STD 32 bus compatible • 8088/8086 code compatible • One 32-pin EPROM socket (480 Kbyte capacity) • Two 32-pin RAM sockets (512 Kbyte capacity) • 32 Kbyte dual port RAM (populated) • Optional battery backup on all RAM • Interrupt controller (V40) • Three 16-bit counter/timers (V40) • Three 8-bit parallel ports, Opto 22 compatible • Two serial ports (V40, 82050), RS-232/422/485 • Two-stage watchdog timer • zSBX expansion module with DMA support •
Introduction Development Considerations Ziatech offers two software development systems for ZT 8832 applications: STD ROM and DOS MPX. STD ROM (Borland’s Turbo Debugger environment using Paradigm Systems’ DEBUG/RT) connects the ZT 8832 to an IBMcompatible personal computer through a high speed serial link. The computer is used as a development station to create, download, and debug applications written in assembly, C, and other high level languages.
Introduction Serial RS-232 (3-Wire) Counter/ Timer and Interrupts Serial RS-232 RS-485 Parallel I/O ZT 8832 NEC V40 Serial Port RS-232 only Serial Port RS-232/ RS-485 Parallel I/O 24-bits Local EPROM 1 Socket Local RAM 2 Sockets Watchdog Timer Lithium Battery DMA Controller Interrupt Controller Counter/ Timers Numeric Data Processor Socket SBX Expansion Module I/O Expansion Socket Dual Port RAM Figure 1–1. Functional Block Diagram.
Introduction FUNCTIONAL BLOCKS Figure 1-1 illustrates the functional blocks of the ZT 8832. A description of each block follows. V40 (µPD70208) Processor The NEC V40 is a highly integrated microprocessor that includes an 8088 compatible CPU and many standard I/O devices. The 8088 compatible CPU executes all code written for the 8088/8086 family of microprocessors. In addition, the V40 instruction set includes expanded rotate and shift, bit and nibble manipulation, and string I/O.
Introduction Dual Port Memory The ZT 8832 is populated with 32 Kbytes of RAM that is accessible from both the local CPU and the STD bus CPU. Arbitration for simultaneous access is done entirely in hardware. To increase system performance, the dual port memory is physically separated from the local memory. This permits the local CPU to continue executing local operations while the STD bus CPU is accessing the dual port memory.
Introduction Serial Communications The ZT 8832 includes two asynchronous serial communication channels, each with a programmable baud rate generator. The V40 provides one serial channel with an architecture similar to the asynchronous portion of the 8251. Configured as RS-232 DTE, this serial channel supports transmit data (TxD), receive data (RxD), and ground. These signals are available through a 3-pin frontplane connector.
Introduction Interrupt Controller The ZT 8832 includes an eight-input programmable interrupt controller with an 8259 architecture. Features of the interrupt controller include level- and edge-triggered sensing, fixed and rotating priorities, and the ability to mask individual inputs. Two of the interrupt request inputs are available through a frontplane connector, to be used as needed by the application.
Introduction zSBX Expansion Module Socket The zSBX expansion module socket is provided to customize the I/O capabilities of the ZT 8832 to the needs of the application. The expansion module interface is electrically, mechanically, and functionally equivalent to the Intel iSBX MULTIMODULE standard, including DMA support for high speed transfers to ZT 8832 memory. This makes hundreds of off-the-shelf modules available to the STD bus designer.
Chapter 2 GETTING STARTED Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 UNPACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 WHAT’S IN THE BOX? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 SYSTEM REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 ZT 8832 Requirements . .
Getting Started UNPACKING Please check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and Ziatech for an insurance settlement. Retain the shipping carton and packing material for inspection by the carrier. Do not return any product to Ziatech without a Return Material Authorization (RMA) number. Appendix C explains the procedure for obtaining an RMA number from Ziatech. WHAT’S IN THE BOX? The items listed below are included in a standard ZT 8832 order.
Getting Started SYSTEM REQUIREMENTS The ZT 8832 is designed for use with or without an STD bus backplane. For STD bus applications, the ZT 8832 is mechanically and electrically compatible with Version 1.1 of the STD 32 Bus Specification and Designer’s Guide. Vertical mounting is recommended in applications not using a fan. Horizontal mounting requires a minimum air flow of 30 cubic feet/min. passing over the surface of the board. Refer to Appendix B for additional specifications.
P1 2-4 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43 W44 W45 W46 ZT 8832 ICP J4 32 KBYTE SRAM STD ROM EPROM W20 W21 W22 W16, W17 W23 W24, W25 W26, W27 W15 W9 W10 W11 W12 W13 W14 W7 W1 W2 W3 W4 W5 W6 W8 J5 J1 J2 J3 Getting Started Figure 2–1. STD ROM Jumper Configuration.
Getting Started INSTALLING THE ZT 8832 WITH STD ROM The fastest way to begin using the ZT 8832 is with the addition of development software from Ziatech. The STD ROM development system connects the ZT 8832 to an IBM-compatible personal computer through a serial link. The personal computer is used as a development station to create, download, and debug applications written in assembly, C, and other high level languages.
Getting Started Jumper Requirements Table 2-1 and Figure 2-1 show the correct jumper positioning for the ZT 8832 configured to support STD ROM. Table 2-1 STD ROM Jumper Configuration. Installed W1-6, 8, 11, 12, 14-16, 21-23, 25, 27, 29, 30, 37, 39, 41-43, 46 Removed W7, 9, 10, 13, 17-20, 24, 26, 28, 31-36, 38, 40, 44, 45 Operation Refer to the STD ROM documentation for software installation and operation procedures.
Getting Started INSTALLING THE ZT 8832 WITH DOS MPX The DOS Multiprocessing Extension (MPX) software provides a development and operating environment for one or more ZT 8832s in a DOS application. DOS MPX allows programmers to develop applications using a high-level language such as C without the problems associated with placing the program in ROM.
Getting Started Jumper Requirements Table 2-2 and Figure 2-2 show the correct jumper positioning for the ZT 8832 configured to support DOS MPX. This is the same jumper configuration required for STD ROM. Table 2-2 DOS MPX Jumper Configuration. Installed W1-6, 8, 11, 12, 14-16, 21-23, 25, 27, 29, 30, 37, 39, 41-43, 46 Removed W7, 9, 10, 13, 17-20, 24, 26, 28, 31-36, 38, 40, 44, 45 Operation Refer to the DOS MPX documentation for software installation and operation procedures.
P1 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43 W44 W45 W46 ZT 8832 ICP J4 32 KBYTE SRAM DOS MPX EPROM W20 W21 W22 W16, W17 W23 W24, W25 W26, W27 W15 W9 W10 W11 W12 W13 W14 W7 W1 W2 W3 W4 W5 W6 W8 J5 J1 J2 J3 Getting Started Figure 2–2. DOS MPX Jumper Configuration.
Getting Started MEMORY The ZT 8832 includes memory that is addressable by the local CPU and memory that is dual ported between the local and STD bus CPU. This is shown in two memory maps: Figure 2-3 illustrates the address ranges of the memory devices available to the local CPU, and Figure 2-4 illustrates the address ranges of the memory devices available to the STD bus CPU. The local ROM is a single memory device located in a 32-pin JEDEC socket.
Getting Started The dual port RAM is a 32 Kbyte RAM populated on the ZT 8832. It is shown on both local and STD bus memory maps because, even through it is the same physical memory, it is accessible from both the local CPU and the STD CPU. The address range of the dual port RAM as seen by the local CPU is fixed from 80000 through 87FFFh. The address range of the dual port RAM as seen by the STD bus CPU is jumper selectable to any 32 Kbyte memory block within a 1 Mbyte address range of an STD bus CPU.
Getting Started I/O The ZT 8832 includes some I/O devices addressable by the local CPU and other I/O devices addressable by the STD bus CPU. This is shown in two I/O maps. Figure 2-6 illustrates the devices accessible by the local CPU. Figure 2-5 illustrates the devices available to the STD bus CPU. Note that none of the I/O devices are accessible from both the local CPU and the STD bus CPU.
Getting Started FFF0-FFFFh V40 Configuration 0400-FFEFh Not Used 03F0-03FFh 82050 Serial Port 0380-03EFh Not Used 0300-037Fh SBX Module - Select 1 0280-02FFh SBX Module - Select 0 0240-027Fh Not Used 0230-023Fh Local Control Port 0220-022Fh Parallel Port 2 0210-021Fh Parallel Port 1 0200-020Fh Parallel Port 0 00E0-01FFh Not Used 00D0-00DFh DMA Controller [1] 00B8-00CFh Not Used 00B0-00B7h V40 Serial Port [1] 0048-00AFh Not Used 0040-0047h Counter/Timers [1] 0028-003Fh Not
Getting Started JUMPER OPTIONS The ZT 8832 includes several jumper options that tailor the operation of the board to the requirements of specific applications. Refer to Appendix A for a description of configurable jumpers.
III. USER’S REFERENCE THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 PROCESSOR DESCRIPTION (V40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 PROCESSOR CONFIGURATION (V40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 COUNTER/TIMERS (V40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3 THEORY OF OPERATION Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 COMMONLY ASKED QUESTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 DUAL PORT MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 STD BUS AND LOCAL CONTROL PORTS . . . . . . . . . . . . . . . . . . . . . . . 3-9 STD Bus Control Port Overview . . . . . . . . . . . . . . . . . . . .
Theory of Operation OVERVIEW This chapter presents a detailed description of ZT 8832 system level operation.
Theory of Operation COMMONLY ASKED QUESTIONS 1. What software development tools are available? Ziatech supports two software development tools for the ZT 8832: STD ROM and DOS Multiprocessing Extension (DOS MPX). The STD ROM software includes a PROM based debugger and a PC based floppy disk. The ZT 8832 is connected to a PC through a serial link. Programs are developed on the PC and transferred across the serial link to the ZT 8832 for debugging.
Theory of Operation 2. Are emulators available for the NEC V40? Yes. Several manufacturers of V40 emulators are listed below. 3-4 Tektronix, Inc. P.O.
Theory of Operation 3. Can the ZT 8832 access STD bus memory and I/O? The ZT 8832 includes 32 Kbytes of dual port RAM mapped into the STD bus memory addressing space. This is the only STD bus memory accessible by the local CPU. The local CPU does not have access to any STD bus I/O. 4. Can the STD bus CPU access memory and I/O local to the ZT 8832? The STD bus CPU has access to 32 Kbytes of dual port RAM local to the ZT 8832. The three 32-pin JEDEC sockets are not available to the STD bus CPU.
Theory of Operation The ZT 8832 is a newer generation board that removes many of the restrictions found on the ZT 8830. The major differences are outlined below. 3-6 • Increased performance. Both the ZT 8830 and ZT 8832 are based on an 8 MHz microprocessor with an 8088 architecture. The major performance increase of the ZT 8832 is realized in the dual port memory design. On the ZT 8830, all local memory is dual ported.
Theory of Operation • 6. More local memory. The ZT 8830 supports a maximum of 32 Kbytes of RAM and 32 Kbytes of EPROM. With memory devices currently available on the market, the ZT 8832 supports 256 Kbytes of RAM and 128 Kbytes of EPROM. When larger devices become available, the ZT 8832 can be expanded to 512 Kbytes of RAM and 480 Kbytes of EPROM. How many ZT 8832s can be used in a system? The number of ZT 8832s is limited by the number of slots in the STD bus card cage and power supply capabilities. 7.
Theory of Operation DUAL PORT MEMORY The ZT 8832 is shipped with 32 Kbytes of dual port RAM. Dual port means that is it accessible by both the ZT 8832 CPU and the STD bus CPU. The dual port memory is physically separate from the ZT 8832 local memory to permit the local CPU to continue operating even during a dual port access by the STD bus CPU. It is not until both CPUs attempt a simultaneous dual port access that arbitration logic suspends the operation of one CPU until the other is completed.
Theory of Operation STD BUS AND LOCAL CONTROL PORTS The STD bus and local control ports increase the control and flexibility of the communication link between the STD bus and the ZT 8832. STD Bus Control Port Overview The STD bus control port is an I/O mapped device programmed by the STD bus CPU to perform the following operations.
Theory of Operation STD Bus Control Port Architecture Figure 3-1 shows the architecture of the STD bus control port. Bit definitions are given on the following pages. Note: Writing a 0Fh followed by a logical 0 to the STD bus control port resets the ZT 8832.
Theory of Operation • Program the interrupt controller to enable IR5, as discussed in Chapter 8; • Remove the hardware mask by programming the LMR bit of the local control port with a logical 0. After the local CPU has performed these operations, the STD bus CPU generates a maskable interrupt to the local CPU by writing a logical 1 to the SMI bit of the STD bus control port.
Theory of Operation The STD Bus Control Port Maskable Interrupt Reset (SMR) bit (bit 3) is programmed by the STD bus CPU to reset an active STD bus maskable interrupt request generated by the local CPU through the LMI bit of the local control port. The Interrupt Status Port (ISP) is available to the STD bus CPU to determine if the local control port LMI bit is active. The STD bus CPU must first program the SMR bit with a logical 0 to enable the local CPU to generate a maskable interrupt.
Theory of Operation Local Control Port Architecture Figure 3-2 shows the architecture of the local control port. Bit definitions are given on the following pages. Note: The STD bus cannot be reset through the local control port. All other functions are symmetrical between the STD bus control port and the local control port.
Theory of Operation writes to the LMI bit are ignored until the interrupt request is cleared by the STD bus CPU writing a logical 1 followed by a logical 0 to the SMR bit of the STD bus control port. The Local Bus Control Port Non-Maskable Interrupt (LNI) bit (bit 1) is programmed by the local CPU to generate a non-maskable interrupt to the STD bus CPU. The local CPU generates a non-maskable interrupt to the STD bus CPU by writing a logical 1 followed by a logical 0 to the LNI bit.
Theory of Operation BOARD SELECT OPTION A ZT 8832 occupies 32 Kbytes of STD bus memory address space and 16 bytes of STD bus I/O address space. The memory is jumper selectable to any 32 Kbyte block and the I/O is jumper selectable to any of 16 possible locations. Systems using multiple ZT 8832s can map each one to a unique memory and I/O address range. However, in some systems this may not be possible because of limited STD bus resources.
Theory of Operation After the above steps are completed, install the ZT 8832s into the STD bus card cage. The ZT 8832s power up not selected. This means that the dual port RAM, STD bus control port, and interrupt status port are not accessible by the STD bus CPU. The Board Select Port is the only port accessible. To begin communicating with a ZT 8832, the STD bus CPU must write the board select address of that ZT 8832 to the Board Select Port (see Figure 3-3).
Theory of Operation STD BUS INTERRUPTS The ZT 8832 is capable of generating maskable and non-maskable interrupts to the STD bus CPU. The maskable interrupt is jumper selectable to the STD bus INTRQ* (pin 44), INTR1* (pin 37), or INTRQ2* (pin 50). The non-maskable interrupt is dedicated to the STD bus NMIRQ* (pin 46). This section discusses the issues surrounding the use of the ZT 8832 and STD bus interrupts.
Theory of Operation The simplest interrupt architecture is one in which the ZT 8832 does not share the interrupt with any other STD bus boards, including other ZT 8832s. For this architecture, an interrupt cycle is outlined below. • The local CPU activates the STD bus interrupt request by writing to the local control port. Please note that the STD bus CPU must first remove the interrupt mask by writing to the STD bus control port.
Theory of Operation The local interrupt status bit (bit 0) indicates the status of the ZT 8832 interrupt request to the STD bus CPU. The STD bus interrupt status bit (bit 1) indicates whether any of the interrupt sources sharing the STD bus interrupt request with the ZT 8832 has an interrupt pending, including the ZT 8832. The following steps outline an interrupt cycle for a shared STD bus interrupt configuration: 1. The local CPU activates the interrupt request by writing to the local control port.
Theory of Operation 7. 3-20 This step applies only to systems with the STD bus CPU configured for edge triggered as opposed to level triggered interrupts. To avoid missing an interrupt request, the interrupt service routine must continue servicing the shared interrupt sources until the STD bus status bit of the ZT 8832 Interrupt Status Port is inactive. This prevents the possibility of missing a request because the edge occurred while servicing another request.
Theory of Operation RESET The ZT 8832 is reset by any of the following events: • Programming the STD bus control port with a 0Fh, followed by a logical 0, from the STD bus CPU. This resets the ZT 8832 only. The STD bus is not affected. • Activating the pushbutton switch located on the ZT 8832. This resets the ZT 8832 only. The STD bus is not affected. • Dropping Vcc applied to the ZT 8832 through pins 3 and 4 of the STD bus connector to below a typical value of 4.37 V (worst case specifications are 4.
Theory of Operation possible for the STD bus CPU to perform these writes as two sequential operations, the SBX expansion module interface requires a 15 µs reset pulse width. In response to all other reset sources, the ZT 8832 enters a reset state that typically lasts 600 ms (worst-case specifications are 250 ms minimum and 1000 ms maximum).
Theory of Operation Table 3-1 includes a list of devices affected by all sources of reset and a page number for a detailed discussion on the reset state of each. Table 3-1 Devices Affected by Reset.
Chapter 4 APPLICATION EXAMPLES Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 EXAMPLE 1: V40 INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Program Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Examples EXAMPLE 1: V40 INITIALIZATION Objectives The ZT 8832 is designed around the NEC 70208 (V40) microprocessor. This high integration microprocessor includes counter/timers, interrupt controller, DMA controller, serial controller, and wait state generator, in addition to a CPU with an 8088 architecture. The V40 also includes programmable configuration registers to provide flexibility when using these devices.
Application Examples Program Code ; EXAMPLE #1 PROGRAMMING ABSTRACT ; ; ; ; Ziatech Corporation San Luis Obispo, CA 06/01/89 ; THIS PROGRAMMING EXAMPLE ILLUSTRATES THE CODE USED BY ; STD ROM TO INITIALIZE THE ; V40 CONFIGURATION REGISTERS.
Application Examples TULA TULA_INIT TCU EQU EQU EQU 0FFF9H ; TULA I/O ADDRESS 40H ; TCU OFFSET ADDRESS 256*OPHA_INIT+TULA_INIT; TCU I/O ADDRESS ; SERIAL CONTROL UNIT SULA EQU SULA_INIT EQU SCU EQU 0FFF8H ; SULA I/O ADDRESS 0B0H ; SCU OFFSET ADDRESS 256*OPHA_INIT+SULA_INIT; SCU I/O ADDRESS RESV2 0FFF7H EQU ; NEC RESERVED ; WAIT REQUEST CONTROL UNIT WCY2 EQU 0FFF6H WCY2_INIT EQU 00001000B WCY1 EQU 0FFF5H WCY1_INIT EQU 10000000B WMB EQU 0FFF4H WMB_INIT EQU 0 ; ; ; ; ; ; RESV3 0FFF3H ; NEC RESERVED
Application Examples STACK SEGMENT STACK STACK_TOP STACK DW LABEL SEGMENT 20 DUP (?) WORD ENDS STACK ; UNINITIALIZED STACK ; TOP OF STACK ; PROCEDURE CODE ASSUME SEGMENT PARA CS:CODE, SS:STACK, DS:NOTHING, ES:NOTHING MAIN: MOV MOV MOV CODE PUT PUT PUT PUT PUT PUT PUT PUT PUT PUT PUT PUT ENDS END BX,SEG STACK SS,BX SP,OFFSET STACK_TOP ; INITIALIZE CONFIG REGS OPCN,OPCN_INIT OPSEL,OPSEL_INIT OPHA,OPHA_INIT DULA,DULA_INIT IULA,IULA_INIT TULA,TULA_INIT SULA,SULA_INIT WCY2,WCY2_INIT WCY1,WCY1_INIT
Application Examples EXAMPLE 2: PERIPHERAL INITIALIZATION Objectives The ZT 8832 contains many of the most commonly used peripherals found in STD bus applications. The following procedures show example initialization sequences for the devices listed below. While these procedures are general purpose in nature, they can be used as a starting point for most application software.
Application Examples ; ; ; ; 82050 SERIAL CONTROLLER V40 SERIAL CONTROLLER AND BAUD RATE TIMER V40 INTERRUPT CONTROLLER V40 DMA CONTROLLER ; SYSTEM EQUATES ; V40 CONFIGURATION REGISTERS OPCN EQU 0FFFEH OPCN_INIT EQU 00000010B OPSEL EQU 0FFFDH OPSEL_INIT_S EQU 00001000B OPSEL_INIT_T EQU 00000100B OPSEL_INIT_I EQU 00000010B OPSEL_INIT_D EQU 00000001B OPHA EQU 0FFFCH OPHA_INIT EQU 0 DULA EQU 0FFFBH DULA_INIT EQU 0D0H IULA EQU 0FFFAH IULA_INIT EQU 20H TULA EQU 0FFF9H TULA_INIT EQU 40H SULA EQU 0FFF8H SULA_I
Application Examples ; V40 SCU SERIAL CONTROLLER AND BAUD RATE TIMER TCU_PORT EQU 256*OPHA_INIT+TULA_INIT ; TCU I/O ADDRESS TCU_TMR1 EQU TCU_PORT+1 ; TIMER 1 CONTROL TCU_TMR1_BD1 EQU 26 ; SCU BAUD OF 9600 TCU_TMR1_BD2 EQU 0 ; TCU_MODE EQU TCU_PORT+3 ; TCU MODE ADDRESS TCU_MODE_INIT EQU 01110110B ; BIN, SQ, 2 BYTE, T1 SCU_PORT EQU 256*OPHA_INIT+SULA_INIT ; SCU I/O ADDRESS SCU_CMND EQU SCU_PORT+1 ; COMMAND ADDRESS SCU_CMND_INIT EQU 00000101B ; ENABLE TXD AND RXD SCU_MODE EQU SCU_PORT+2 ; MODE ADDRESS SCU_MODE
Application Examples MACRO DEFINITIONS PUT MACRO MOV MOV OUT ENDM SRCE,DATA DX,SRCE AL,DATA DX,AL ; I/O WRITE MACRO ; STACK SEGMENT STACK STACK_TOP STACK DW LABEL SEGMENT 20 DUP (?) WORD ENDS STACK ; UNINITIALIZED STACK ; TOP OF STACK ; DATA SEGMENT ; THIS DATA SEGMENT PROVIDES A DATA BUFFER FOR DMA OPERATIONS ; BETWEEN THE SBX EXPANSION MODULE I/O AND LOCAL RAM.
Application Examples PARALLEL PORT PROCEDURE ; ; THE ZT 8832 INCLUDES THREE PARALLEL PORTS. THE PARALLEL PORT ; OUTPUTS ARE ENABLED AND DISABLED WITH THE OUT2 BIT OF THE ; 82050 SERIAL PORT TO PREVENT GLITCHES DURING POWER-UP. THE ; POWER-UP STATE OF OUT2 IS A LOGICAL 0 THAT DISABLES THE ; PARALLEL PORT OUTPUTS. PASSIVE TERMINATION MAINTAINS A TTL ; HIGH ON THE PARALLEL I/O SIGNALS AT CONNECTOR J1 WHEN THE ; PARALLEL PORTS ARE DISABLED.
Application Examples LED PROCEDURE ; ; ; ; ; ; ; ; ; THE LED CAN BE TURNED ON AND OFF UNDER SOFTWARE CONTROL. THIS IS A VALUABLE STATUS INDICATOR, ESPECIALLY DURING THE DEBUG PHASE OF APPLICATION DEVELOPMENT. THE FOLLOWING CODE SHOWS THE PROCEDURE FOR ARMING THE LED AND TURNING IT ON AND OFF.
Application Examples ; ; ; ; ; INPUTS: OUTPUTS: CALLS: DESTROYS: LED_OFF NONE LED IS TURNED OFF NONE FLAGS PROC ; PRESERVE REGISTER STATUS PUSH PUSH MOV IN AND OUT POP POP ENDP LED_OFF AX DX ; TURN OFF THE LED DX,PAR_PORT_2 AL,DX AL,NOT PAR_PORT_LED DX,AL ; RESTORE THE REGISTER STATUS DX AX ; 82050 SERIAL CONTROLLER PROCEDURE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; THE 82050 SERIAL CONTROLLER IS A PC COMPATIBLE ASYNCHRONOUS COMMUNICATION CHANNEL SUPPORTING JUMPER SELECTABLE DCE/DTE AND RS-232/RS-485 CO
Application Examples PUT PUT ACC_INIT POP POP ENDP ACC_MODC,ACC_MODC_INIT ; MASK INTERRUPTS ACC_INTC,ACC_INTC_INIT ; RESTORE REGISTER CONTENTS DX AX ; V40 SERIAL CONTROLLER PROCEDURE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; THE V40 SERIAL CONTROLLER IS AN 8251 COMPATIBLE ASYNCHRONOUS COMMUNICATION CHANNEL CONFIGURED AS THREE-WIRE (TRANSMIT DATA, RECEIVE DATA, AND GROUND) RS-232 DTE.
Application Examples PUT PUT SCU_INIT POP POP ENDP SCU_CMND,SCU_CMND_INIT ; MASK INTERRUPTS SCU_MASK,SCU_MASK_INIT ; RESTORE REGISTER STATUS DX AX ; V40 INTERRUPT CONTROLLER PROCEDURE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; THE V40 INTERRUPT CONTROLLER IS USED TO SERVICE ASYNCHRONOUS EVENTS SUCH AS A COUNTER/TIMER TIMEOUT, DATA TRANSFERS THROUGH A SERIAL LINK, AND DATA TRANSFERS THROUGH DUAL PORT RAM.
Application Examples PUT ICU_INIT POP POP ENDP ICU_MASK,ICU_MASK_INIT ; RESTORE THE REGISTER STATUS DX AX ; V40 DMA CONTROLLER PROCEDURE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; THE V40 DMA CONTROLLER IS USED FOR HIGH SPEED DATA TRANSFERS BETWEEN AN SBX EXPANSION MODULE THAT SUPPORTS DMA AND EITHER DUAL PORT OR LOCAL RAM. THE APPROXIMATE DATA RATE FOR TRANSFERS BETWEEN THE EXPANSION MODULE AND RAM USING STANDARD INPUT AND OUTPUT INSTRUCTIONS IS 235 KBYTES PER SECOND.
Application Examples ; ; ; ; ; ; ; ; ; SINGLE BYTE TRANSFERS INCREMENT MEMORY ADDRESS SBX I/O TO RAM OPERATION INPUTS: OUTPUTS: CALLS: DESTROYS: DCU_WRITE NONE SBX I/O TO RAM MEMORY TRANSFERS ARMED NONE FLAGS PROC ; PRESERVE REGISTER STATUS PUSH PUSH PUSH PUSH MOV MOV MOV MOV SHL SHR ADD ADC MOV MOV OUT MOV MOV OUT MOV MOV OUT PUT PUT DCU_WRITE POP POP POP POP ENDP AX BX CX DX ; SET UP ADDRESS REGISTERS AX,SEG DATA DX,OFFSET DMA_BUF BL,AH CL,4 AX,CL BL,CL DX,AX BL,0 AX,DX DX,DCU_DBA_OFF DX,AX AX,BX DX
Application Examples ; CALLS: ; DESTROYS: NONE FLAGS DCU_READ PROC ; PRESERVE REGISTER STATUS PUSH PUSH PUSH PUSH MOV MOV MOV MOV SHL SHR ADD ADC MOV MOV OUT MOV MOV OUT MOV MOV OUT PUT PUT POP POP POP POP DCU_READ CODE POP POP POP ENDP ENDS END AX BX CX DX ; SET UP ADDRESS REGISTERS AX,SEG DATA DX,OFFSET DMA_BUF BL,AH CL,4 AX,CL BL,CL DX,AX BL,0 DX,DCU_DBA_OFF AX,DX DX,AX DX,DCU_DBA_SEG AX,BX DX,AL ; SET UP COUNT REGISTERS AX,SIZE DMA_BUF DX,DCU_DBC DX,AX ; SET UP MODE AND ENABLE DCU_DMD,DCU_DMD_READ
Application Examples EXAMPLE 3: WATCHDOG TIMER Objectives A watchdog timer is useful in applications in which a microprocessor controls a physical process that may be damaged if the microprocessor fails to function as programmed. The ZT 8832 includes a jumper selectable watchdog timer which monitors operation of the V40 and initiates corrective action if necessary. As discussed in Chapter 13, the watchdog timer has two stages.
Application Examples Program Code ; EXAMPLE #3 PROGRAMMING ABSTRACT ; ; ; Ziatech Corporation San Luis Obispo, CA 06/01/89 ; THIS PROGRAMMING EXAMPLE ILLUSTRATES THE CODE USED TO ARM AND ; STROBE THE WATCHDOG TIMER. ALSO INCLUDED IS A NON-MASKABLE ; INTERRUPT SERVICE ROUTINE THAT FLAGS A WATCHDOG TIMEOUT IN ; DUAL PORT RAM. NOT SHOWN IS THE ZT 8832 STARTUP CODE THAT ; TESTS THE FLAG LOCATION TO SEE WHETHER THE RESET WAS CAUSED ; BY A WATCHDOG TIMEOUT OR BY ANOTHER SOURCE OF RESET.
Application Examples STACK SEGMENT STACK STACK_TOP STACK DW LABEL SEGMENT 20 DUP (?) WORD ENDS STACK ; UNINITIALIZED STACK ; TOP OF STACK ; DATA SEGMENT ; A MULTIPLE CHARACTER FLAG IS USED TO REDUCE THE CHANCE THAT ; THE ZT 8832 STARTUP CODE (NOT SHOWN HERE) WILL FALSELY DETECT ; A WATCHDOG TIMER RESET AFTER A POWER CYCLE.
Application Examples TYPE_1 TYPE_2 INT_POINT DD DD ENDS ? ? ; SINGLE STEP (NOT USED) ; NON-MASKABLE INTERRUPT PROCEDURES CODE ASSUME ; ; ; ; ; ; ; ; ; ; ; ; ; ; SEGMENT PARA CS:CODE, SS:STACK, DS:DATA, ES:DUALPORT THE WATCHDOG TIMER GENERATES A NON-MASKABLE INTERRUPT IF ARMED AND ALLOWED TO TIME OUT. THE TASKS PERFORMED BY THE SERVICE ROUTINE ARE VERY APPLICATION SPECIFIC. THIS EXAMPLE SIMPLY SETS A FLAG IN DUAL PORT RAM AND LOOPS UNTIL RESET.
Application Examples WATCHDOG_STB AND OUT OR OUT POP POP RET ENDP AL, NOT PAR_PORT_WD DX,AL AL,PAR_PORT_WD ; WRITE WATCHDOG BIT HIGH DX,AL DX ; RESTORE REGISTER STATUS AX ; EXIT ; ; ; ; ; ; ; ; ; ; ; ; ; ; NONE NONE WATCHDOG_STB ALL THE MAIN PROCEDURE INCLUDES A LOOP AND A CALL TO THE WATCHDOG STROBE PROCEDURE. THE LOOP REPRESENTS THE APPLICATION SOFTWARE. IN NORMAL OPERATION, THE WATCHDOG STROBE PROCEDURE IS CALLED AT A PERIODIC RATE LESS THAN THE WATCHDOG TIMER STAGE 1 DELAY OF 60 MILLISECONDS.
Application Examples LP3: CODE LOOP CALL JMP ENDS END LP3 WATCHDOG_STB LP2 ; STROBE WATCHDOG TIMER ; REPEAT MAIN 4-23
Chapter 5 PROCESSOR DESCRIPTION (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 COMMONLY ASKED QUESTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 CPU - Central Processing Unit .
Processor Description (V40) OVERVIEW The NEC 70208, commonly known as the V40, is a CMOS microprocessor with a 16-bit internal and 8-bit external data bus structure. The V40 instruction set includes all of the instructions of the 8088 and 80188 microprocessors, plus a few more. The added instructions include string I/O, expanded rotate and shift, bit and nibble manipulation, BCD arithmetic, and 8080 emulation mode. The V40 contains several peripherals frequently used in STD bus applications.
Processor Description (V40) COMMONLY ASKED QUESTIONS 1. Is the V40 pin-compatible with the 80188? The V40 and 80188 are not pin-compatible. This means an 80188 cannot be plugged into the V40 socket. This is unlike the V20 and V30, which are interchangeable with the 8088 and 8086, respectively. 2. What are the hardware differences between the V40 and the 80188? One of the most notable differences is that the V40 is fabricated with a CMOS process.
Processor Description (V40) these microprocessors, plus a few more. The added instructions are outlined below. The following instructions are useful in testing and setting status bits for I/O operations and in bit manipulation for graphics applications. INS EXT TEST1 SET1 CLR1 NOT1 Insert bit field Extract bit field Test bit Set bit Clear bit Complement bit The instructions shown below are useful for manipulating binary numbers in a decimal format.
Processor Description (V40) FUNCTIONAL BLOCKS The V40 can be divided into the major functional blocks listed below and shown in Figure 5-1 on page 5-6.
Processor Description (V40) CPU - Central Processing Unit The architecture of the CPU functional block is compatible with the 8088. The CPU recognizes all of the instructions found in the 8088 and 80188 microprocessors. Figure 5-2 shows a block diagram of the CPU divided into two elements: the Bus Control Unit (BCU) and the Execution Unit (EXU). The BCU prefetches instructions and data into a 4-byte instruction queue. The EXU executes the instructions.
Processor Description (V40) Internal address/data bus (20) TO BIU ADM BCU PS [CS] SS [SS] DS0 [DS] DS1 [ES] PFP [IP] DP Q0-Q3 AW [AX] BW[BX] CW [CX] DW [DX] SP [SP] BP [BP] IX [SI] IY [DI] PC LC EXU TA, TB, AND TC ALU PSW [FL] Effective Address Generator Subdata bus (16) Main data bus (16) Figure 5–2. CPU Block Diagram.
Processor Description (V40) CPU Functional Blocks The functional blocks in Figure 5-2 are described below. The NEC mnemonic is shown for each block, followed by the Intel mnemonic in brackets. For example, the CPU flag register is represented by PSW [FL] because NEC labels it Processor Status Word and Intel labels it Flags. Segment Registers PS [CS], SS [SS], DS0 [DS], and DS1 [ES] The CPU can address up to 1 Mbyte of memory in segments of 64 Kbytes or less.
Processor Description (V40) Strings are addressed differently from other variables. The segment register used to point to the source string is DS0 [DS], unless an override is used. The offset for the string source is the IX [SI] register. The segment register for the string destination is always DS1 [ES] and the offset is specified in IY [DI]. Table 5-1 Segment Registers.
Processor Description (V40) For sequentially addressed instructions, the PFP [IP] is incremented by the number of bytes of the current instruction to point to the next. For program branching, such as intrasegment and intersegment jumps, the PFP [IP] is programmed with a value contained within the jump instruction. The PFP [IP] is not accessible to the programmer. Data Pointer DP This 16-bit register is the destination for the offset address calculated by the effective address generator.
Processor Description (V40) General Purpose Registers AW [AX], BW [BX], CW [CX], and DW [DX] The CPU has four 16-bit general purpose registers. Each of these registers can be addressed as one 16-bit register or two 8-bit registers. The 16-bit registers are referred to as AW [AX], BW [BX], CW [CX], and DW [DX]. The high order bytes of the 16bit registers are AH, BH, CH, and DH, while the low order bytes are AL, BL, CL, and DL.
Processor Description (V40) Pointers and Index Registers SP [SP], BP [BP], and IX [SI], IY [DI] The two 16-bit pointer registers are used primarily for stack operations. The Stack Pointer (SP [SP]) is the offset to the top of the stack within the stack segment. This pointer is adjusted automatically each time a stack operation is performed. The Base Pointer (BP [BP]) is an offset to any location within the stack segment. The BP [BP] is useful as a pointer to variables being passed on the stack.
Processor Description (V40) Loop Counter LC LC is a binary counter used to regulate iterative operations such as string transfers controlled by the repeat prefix and multiple-bit shifts and rotations. The CPU uses hardware for a loop counter, as opposed to microcode used by the traditional microprocessor. Temporary Registers A, B, and C TA, TB, and TC These 16-bit registers are used by the ALU during arithmetic and logical instructions such as multiplication, division, and shift and rotate.
Processor Description (V40) 12 clocks to calculate the effective address using microcode. However, the V40 does all effective address calculations in two clocks with the hardware EAG. The effective address, once calculated by the EAG, is transferred to the DP register, where it can be used by the BCU to transfer data between the CPU and memory. Program Status Word PSW [FL] There are six status flags and four control flags in the 16-bit PSW [FL], as seen in Figure 5-3.
Processor Description (V40) The control flags are used by the programmer to direct CPU operation. The control flags are set (logical 1) and reset (logical 0) with dedicated instructions. The IE [IF] and BRK [TF] flags are automatically reset when the program enters an interrupt service routine.
Processor Description (V40) number of bits set. This flag is useful for checking the parity of ASCII characters. AC [AF] (Auxiliary Flag) - AC [AF] is set if an addition results in a carry from the four least significant bits of the result. This is true for both byte and word addition. This flag is used by the CPU for BCD arithmetic operations. Z [ZF] (Zero Flag) - Z [ZF] is set if the result of an arithmetic or logical operation is zero. A common use of this flag is to determine if two numbers are equal.
Processor Description (V40) the array during a string operation. After a string operation is completed, the index registers are incremented or decremented, depending on the state of the DIR [DF] flag. If the DIR [DF] flag is set, the index is incremented to point to the next array element. If the DIR [DF] flag is reset, the index is decremented. IE [IF] (Interrupt Enable Flag) - The IE [IF] flag determines how the CPU responds to maskable external interrupts.
Processor Description (V40) Enhanced Architecture The V40 CPU includes several enhancements that provide an increase in performance over the 8088 microprocessor found on many STD bus designs. The most noticeable performance improvements come from additional hardware for the Effective Address Generator, Loop Counters and Shifters, and the use of dual internal data buses.
Processor Description (V40) BIU - Bus Interface Unit The BIU controls the external address, data, and control buses. The BIU also synchronizes the RESET and READY inputs with the clock, as shown in Figure 5-4. The synchronized RESET signal is used internally. It is provided externally as a signal called RESOUT. The synchronized READY signal is combined with the output of the Wait Control Unit to control the number of wait states inserted during bus operations.
Processor Description (V40) the buses at any given time. The bus masters are prioritized in the following order: (1st) DCU - DMA Control Unit (2nd) HLDRQ - External Bus Master (3rd) CPU - Central Processing Unit If the bus is being used by one bus master and another with higher priority makes a request, the BAU inactivates the current bus master’s acknowledge. The BAU grants access to the higher priority bus master after the current bus master removes the request.
Processor Description (V40) WCU - Wait Control Unit The WCU provides added flexibility for interfacing to memory and I/O that have varying speed requirements. The V40 includes three internal bus masters that access memory and I/O devices. The number of wait states inserted can be programmed separately for the CPU, RCU, and DCU. The memory space can be divided into three separate areas and the number of wait states defined differently for each.
Processor Description (V40) ICU - Interrupt Control Unit Interrupts provide an efficient interface between the V40 CPU and supporting peripheral devices. The ICU supports eight interrupts directly and can be cascaded with other interrupt controllers, such as the 8259A Programmable Interrupt Controller, to support additional interrupting sources. Programming the ICU is similar to programming the 8259A. DCU - DMA Control Unit The DCU controls high speed data transfer between I/O and memory devices.
Processor Description (V40) RESET Resetting the V40 initializes registers internal to the CPU, VCR, SCU, TCU, ICU, and DCU. The reset states for the CPU registers are given in Table 5-3. Reset states for registers internal to the VCR, TCU, ICU, DCU, and SCU are given in their respective chapters. The reset states of the program segment and instruction pointer combine to produce a physical address of FFFF0h. This is the address from which the V40 fetches the first instruction after reset.
Processor Description (V40) MEMORY AND I/O ADDRESSING This section discusses how the V40 communicates with memory and I/O devices. The V40 has a 20-bit address bus and an 8-bit data bus. With 20 bits of address, the V40 can directly access up to 1 Mbyte of memory. The address range is from 0 to FFFFFh, as shown in Figure 5-5. Address locations 0 to 7Fh are reserved for dedicated interrupts and future enhancements.
Processor Description (V40) To the programmer, the V40 address space is organized as a contiguous sequence of up to 1 Mbyte. Data can be addressed in units of bytes, words, and double words. Word and double word values are stored in memory with the most significant byte at the higher address and the least significant at the lower. Figure 5-6 illustrates these data formats. N 7 0 Byte Data N+1 N 15 8 7 0 Word Data N+3 31 24 N+2 23 16 N+1 15 8 7 0 N Double Word Data Figure 5–6.
Processor Description (V40) The lower 16 of the 20 address lines are also used to address I/O devices. With 16 bits of address, the V40 can directly access up to 64 Kbytes of I/O. The address range is from 0 to FFFFh, as shown in Figure 5-7. Address locations FF00 through FFEFh are reserved for future use. The address range from FFF0 through FFFFh is currently used for the V40 configuration registers.
Processor Description (V40) INTERRUPTS The V40 includes a versatile interrupt structure that supports both hardware and software initiated interrupts. Hardware interrupts are external inputs to the V40 and can be classified as maskable or nonmaskable. Maskable interrupts are routed to the CPU through the ICU. The ICU provides the maskable interrupt inputs with the ability to be level- or edge-triggered, have fixed or rotating priorities, and be individually masked.
Processor Description (V40) Table 5-4 Interrupt Sources.
Processor Description (V40) The purpose of an interrupt is to redirect the CPU from its current activity to an interrupt service routine designed to handle the needs of the interrupting source. Every interrupting source is associated with a number that points the CPU to a location in memory that contains the address of the interrupt service routine. This number is called an interrupt vector.
Processor Description (V40) The vector of an interrupt source must be known before the location of the service routine address can be determined. The interrupt vector table, shown in Table 5-5, lists the vectors for the sources of interrupts. As an example, assume you need to write a service routine to handle a non-maskable interrupt (NMI) request. The vector for NMI is two, as seen in the Table 5-5.
Processor Description (V40) Before describing each source of interrupt shown in the vector table, it is useful to summarize the operation of the CPU in response to an interrupt. Interrupts come to the CPU from three sources: the NMI signal external to the V40, the output of the ICU, and from inside to the CPU itself. A vector is supplied in all cases to distinguish between the interrupting sources. The CPU determines the address of the service routine by multiplying the vector times four.
Processor Description (V40) CPU restores the PSW [FL], PS [CS], and PSP [IP]. The single-step interrupt is not masked by the IE [IF] bit in the PSW [FL]. Non-Maskable The V40 has a non-maskable interrupt input called NMI. NMI is rising edge triggered but must remain active for two CPU clocks to guarantee recognition. This interrupt is not maskable and the vector is fixed at 2.
Processor Description (V40) Check Index The purpose of the check index instruction is to test the index of an array against an upper and lower limit. The CHKIND [BOUND] instruction generates a check index interrupt if the index value is less than the lower limit or greater than the upper limit. The vector for the check index instruction is fixed at 5 and is not maskable.
Processor Description (V40) 8080 EMULATION Designs based on 8080 and 8085 microprocessors have two major limitations: inadequate performance and lack of development tools. Upgrading an 8-bit design to a higher performance microprocessor requires time to convert the software. The V40 solves these problems by supporting two modes of operation: emulation mode and native mode. When the CPU is in emulation mode, it executes the 8080 instruction set. Emulation mode is used for the existing software base.
Processor Description (V40) A hardware interrupt suspends the 8080 emulation mode. The CPU pushes the PSW [FL] and return address onto the native mode stack, sets the MD flag to a logical 1, and transfers program execution to the native mode interrupt service routine. When the CPU executes the RETI [IRET] instruction, the PSW [FL] is restored with the MD flag set to a logical 0, and program execution continues in the emulation mode.
Processor Description (V40) Emulation mode uses the BP [BP] register for the stack pointer, rather than the native mode SP [SP] register, to reduce the possibility of programming errors in one mode corrupting the stack of the other. This feature is helpful during program development. Table 5-6 Emulation Mode Registers and Flags.
Chapter 6 PROCESSOR CONFIGURATION (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 VCR - V40 CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . 6-2 OPCN - On Chip Peripheral Connection Register . . . . . . . . . . . . . . . . 6-3 OPSEL - On Chip Peripheral Selection Register . . . . . . . . . . . . . . . . . 6-4 OPHA, DULA, IULA, TULA, and SULA . . . . . . . . . . . . . . . . . . . . . . .
Processor Configuration (V40) VCR - V40 CONFIGURATION REGISTERS The 12 V40 configuration registers are mapped from I/O address FFF0h through FFFFh. The registers are listed in Table 6-1 and are discussed in detail on the following pages. All of the registers can be written to with the output instruction and read from with the input instruction. The value input may be different from the value output, but only in the bits not defined. Table 6-1 V40 Configuration Registers.
Processor Configuration (V40) OPCN - On Chip Peripheral Connection Register Figure 6-1 shows the OPCN register. Bit 0 must be programmed with a logical 0 and bit 1 must be programmed with a logical 1. The two bits of the IRSW field select the interrupt source to be assigned to IRQ1 and IRQ2 of the interrupt controller. The values programmed into bits 2 and 3 depend on the use of the interrupt controller in the application.
Processor Configuration (V40) OPSEL - On Chip Peripheral Selection Register The V40 integrates several of the most common peripheral devices with a CPU in one package. The peripheral devices include a serial port, an interrupt controller, a DMA controller, and three counter/timers. The OPSEL register enables or disables these peripheral devices. The format of the OPSEL register is shown in Figure 6-2. No restrictions are placed on the use of the OPSEL register.
Processor Configuration (V40) OPHA, DULA, IULA, TULA, and SULA Five registers determine the I/O base address of the programmable registers used to communicate with the DMA controller, interrupt controller, timer/counters, and serial controller.
Processor Configuration (V40) The only restriction placed on programming these registers is to be sure the peripherals internal to the V40 are not mapped in the same address range as other I/O devices local to the ZT 8832. The STD ROM software programs these registers with the values shown in Table 6-2. Table 6-2 STD ROM Programmable Address Selection.
Processor Configuration (V40) WCY2 - Wait Cycle 2 Register The V40 includes a programmable wait-state generator that interfaces to memory and I/O devices that are not fast enough to operate without wait states. The wait-state generator is programmed through the WCY2, WCY1, and WMB configuration registers. The format of the WCY2 register is shown in Figure 6-3. Bit 2 must be programmed with a logical 0 and bit 3 must be programmed with a logical 1 to select two wait states into DMA cycles.
Processor Configuration (V40) The ZT 8832 does not require any memory wait states if memory devices with access times less than 250 ns are used. To select zero memory wait states, program bits 0 through 5 with logical 0s. Programming bit 6 with a logical 0 and bit 7 with a logical 1 selects the two I/O wait states required by peripherals on the ZT 8832. The STD ROM software programs the WCY1 register with an 80h.
Processor Configuration (V40) WMB - Wait Memory Boundary Register The ZT 8832 does not require any wait memory wait states if memory devices with access times less than 250 ns are used. If slower memory devices are used, the WMB register divides the ZT 8832 memory into three regions and the WCY1 register defines the number of wait states inserted into each. As shown in Figure 6-5, the WMB register is divided into Upper Memory Boundary (UMB) and Lower Memory Boundary (LMB) fields.
Processor Configuration (V40) The Middle Memory Block is defined between the top of the LMB and the bottom of the UMB. Offboard memory (STD bus) requires one wait state in all cases and is defined by the MMB. The LMB field defines the lower memory address range starting from zero. This field can be programmed to include the memory devices inserted into the RAM LOW and RAM HIGH sockets. The UMB field defines the upper memory address range ending at FFFFFh.
Processor Configuration (V40) The CS0, CS1, and CS2 (Clock Select 0, 1, and 2) bits select the counter/timer clock source to be either the reference clock internal to the V40 or the TCLK pin available on an external V40 pin. The V40 clock operates at 8 MHz with a 50% duty cycle. The TCLK signal is available through connector J3. The Prescale (PS) field selects a prescale value that divides the clock frequency of all counter/timers using the V40 internal clock, then applies that value to the counter/timers.
Processor Configuration (V40) RESET The V40 configuration registers are automatically initialized to a default state when power is applied to the V40 and also during reset from an external source. Table 6-3 shows the default state of the configuration registers. Table 6-3 V40 Configuration Register Defaults.
Chapter 7 COUNTER/TIMERS (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Mode Register . . . . . .
Counter/Timers OVERVIEW This chapter describes the Counter/Timer Control Unit (TCU) and provides register descriptions. The TCU includes three 16-bit programmable counter/timers. Applications for the counter/timers include baud rate generation for the serial controller, timing loops, timed and periodic interrupts, and asynchronous event counters.
Counter/Timers ZT 8832 SPECIFICS The clock source for each counter/timer is defined in the TCKS V40 configuration register. Choices for the clock source are either the V40 internal clock or the TCLK signal. The clock internal to the V40 has a frequency of 8 MHz and a duty cycle of 50%. The TCLK signal is available through connector J3.
Counter/Timers FUNCTIONAL DESCRIPTION The TCU is similar to the 8254 Programmable Interval Timer in that the programmable registers are the same. Some restrictions apply to the operating modes of individual counter/timers because they are connected to the V40 internally and external control inputs are not available. These restrictions are discussed below in an explanation of individual operating modes. Figure 7-1 illustrates the major functional blocks of the TCU.
Counter/Timers Mode Register The 8-bit Mode register is programmed to control the operation of the counter/timers. Clock Select and Divisor The difference between a timer and a counter is the clock source. The clock source for a timer is periodic, while the clock source for a counter is usually not periodic. A timer is used to reduce the frequency of a periodic signal; a counter is used to monitor the occurrence of asynchronous events.
Counter/Timers The Count register and Count Latch are the interface through which the count data is transferred between the TCU and the CPU. The Count register receives the count value programmed to the TCU. The count value can be either 8 bits or 16 bits. Eight-bit values can be specified as either upper or lower bytes. A useful feature of counter/timers is that they can be read at any time.
Counter/Timers PROGRAMMABLE REGISTERS Four separately addressable registers are used for communication with the TCU. The TMD (Timer Mode) register specifies the operation of the three counter/timers. The TMD is a write-only register. The other three bidirectional registers, called the Count and Status registers, are used to write the count to the counter/timers and read the count and status back. The base I/O address of the TCU registers is defined by the OPHA and TULA registers.
Counter/Timers Timer Mode Register (TMD) The counter/timers must be initialized with the 8-bit TMD register. The three formats for the TMD register are shown in Figures 7-2, 7-3, and 7-4 (pages 7-9 to 7-11). The General Mode format is programmed initially to define the operation of the counter/timers. The Count Latch Mode and Multiple Latch Mode are programmed at any time to read the count and status data while the counter/timers are operating.
Counter/Timers A new count can be written into the counter/timers at any time without reprogramming the TMD register. Care must be taken to be consistent with the Read/Write Mode each time the new count is programmed. As an example, assume that counter/timer 0 is programmed with a Read/Write Mode of two bytes. Two bytes must be written to counter/timer 0 each time a new count is specified. The same applies for reading counter/timer 0; that is, two count bytes must be read at a time.
Counter/Timers Each counter/timer must be programmed to operate in one of six possible count modes. Selection of the count mode is based on the needs of the application. The counting operation of each counter/timer is programmed as either binary or Binary-CodedDecimal (BCD). The range of a counter/timer programmed for binary operation is 0 to FFFFh, while the BCD operation range is 0 to decimal 9999.
Counter/Timers Multiple Latch Mode Programming the Select Counter bits of the TMD to logical 1s defines the Multiple Latch command (see Figure 7-4). The CNT0, CNT1, and CNT2 bits select which of the counter/timers will be latched. The Status Latch and Count Latch bits determine whether the status, the count, or both are to be latched. The status must be latched to be read. The count can be read without being latched, but will be invalid if it is changing at the time of the read.
Counter/Timers Count Registers The Count register is illustrated in Figure 7-5. Unlike the Mode register, there is one Count register for each of the three counter/timers. The Count register transfers count values to and from the Down Counter. The 16-bit register is programmed with a high byte, low byte, or both high and low byte, as specified with the Read/Write Mode bits in the Mode register. If the high byte or low byte mode is selected, only one read or write operation is needed for data transfers.
Counter/Timers The Multiple Latch command must be used to read the status. The number of required read operations depends on the Read/Write Mode and the Multiple Latch command. If the Read/Write Mode is high byte or low byte and only the status is latched with the Multiple Latch command, one read operation is all that is needed. Two reads are required if both the status and the count are latched by the Multiple Latch command. The first read is for the status and the second is for the data.
Counter/Timers OPERATION Reset The TCU registers are not initialized to a default state after power on or reset. Count Latch Command The count of any counter/timer can be read at any time. The Count Latch command must be used to guarantee accurate results. Without the Count Latch command, the count may change during the read operation and the data will be undefined. After the latch command is specified in the Mode register, the present value of the Down Counter is latched into the Count Latch.
Counter/Timers Multiple Latch Command The Multiple Latch command extends the capabilities of the Count Latch command. The Multiple Latch command is used to selectively latch the count and status of any or all counter/timers simultaneously. This command is the only method of reading the status of a counter/timer. Once the status or count is latched with this command, it is unaffected by further latch commands.
Counter/Timers Modes of Operation There are six possible count modes for the counter/timers. There are restrictions for counter/timers 0 and 1 because the control inputs are not available externally. Mode 0 - Interrupt on Count Termination In Mode 0 operation, the counter/timers count down the programmed number of counts and transition the output signal. This mode is commonly used to count external events.
Counter/Timers The TCTL signal is used to enable and disable the counting operation. The counting operation is enabled if TCTL is high and disabled if TCTL is low. TCTL has no effect on the TOUT signal. The Down Counter does not begin decrementing until the clock pulse after the count is programmed. This is because it takes one clock pulse to transfer the count from the Count register to the Down Counter.
Counter/Timers Mode 1 - Retriggerable One-Shot In Mode 1, counter/timer 2 is triggered to generate a pulse of programmed length. Applications can use this mode to signal the occurrence of a single external event without having to monitor for a change in count. This mode is supported only by counter/timer 2. Examples of Mode 1 operation are shown in Figure 7-8. TOUT is high until one clock pulse after TCTL triggers the count operation to start. This is the start of the one-shot pulse.
Counter/Timers CLK COUNT = 0002H IOWR (Internal) TCTL2 TOUT2 Count value ? ? ? IOWR COUNT = 0005H 0002H 0001H 0000H FFFFH 0002H 0001H 0002H 0003H 0002H 0000H FFFFH COUNT = 0003H (Internal) TCTL2 TOUT2 Count value ? ? ? 0005H 0004H 0003H 0001H 0000H Figure 7–8. Mode 1 Operation.
Counter/Timers Mode 2 - Rate Generator The output of a counter/timer in Mode 2 is high until the programmed count reaches one, then pulses low for a single count before returning to a high value and repeating the operation. Counter/timer 2 fully supports Mode 2 operation with TCTL available through connector J3 of the ZT 8832. Counter/timers 0 and 1 support Mode 2 with the exception of the TCTL input.
Counter/Timers CLK COUNT = 0003H IOWR (Internal) TCTL2 TOUT2 Count value ? ? 0003H 0002H IOWR COUNT = 0006H 0001H 0003H 0002H 0002H 0003H 0002H 0001H 0004H 0001H COUNT = 0004H (Internal) TOUT2 Count value ? ? 0006H 0005H 0004H 0003H 0002H 0003H 0002H Figure 7–9. Mode 2 Operation.
Counter/Timers Mode 3 - Square Wave Generator The most common use for Mode 3 is baud rate generation. The V40 Serial Control Unit requires that counter/timer 1 be configured in Mode 3 to provide the serial transmit and receive clock. The only difference between Mode 2 and Mode 3 is the duty cycle of the counter/timer output. In Mode 2, the output pulses low for the last count, while in Mode 3 the output is low for half of the programmed count.
Counter/Timers Actual counter operation is different for even and odd counts. For even counts, the initial count is loaded in one clock pulse and decremented by two on succeeding clock pulses. TOUT changes state when the count expires and the operation is repeated. For odd counts, the initial count minus one is loaded in one clock pulse and decremented by two on succeeding clock pulses. TOUT goes low one clock pulse after the count expires and the operation is repeated.
Counter/Timers Mode 4 - Software Triggered Strobe Mode 4 operation provides a means of generating a hardware delay triggered by software. Counter/timer 2 fully supports Mode 4 operation with the TCTL input available through connector J3 of the ZT 8832. Counter/timers 0 and 1 support Mode 4 with the exception of the TCTL input signal. Examples of Mode 4 operation are included in Figure 7-11. Counting begins automatically one clock pulse after the count is programmed.
Counter/Timers CLK COUNT = 4 IOWR (Internal) TOUT2 Count value ? ? 0004H 0003H 0002H 0001H 0000H FFFFH FFFEH FFFDH FFFCH ? ? 0004H 0004H 0004H 0003H 0002H 0001H 0000H FFFFH FFFEH 0003H 0002H 0001H 0000H FFFFH IOWR (Internal) TCTL2 TOUT2 Count value IOWR COUNT = 5 COUNT = 3 (Internal) TOUT2 Count value ? ? 0005H 0004H 0003H 0002H Figure 7–11. Mode 4 Operation.
Counter/Timers Mode 5 - Hardware Triggered Strobe Mode 5 operation provides a means of generating a hardware delay triggered by a hardware signal. This mode is similar to Mode 4 except for the counting process, which is started by a signal external to the ZT 8832. Counter/timer 2 is the only one that supports Mode 5. Examples of Mode 5 operation are illustrated in Figure 7-12. A TCTL trigger transfers the programmed count from the Count Latch to the Down Counter and starts the counting process.
Counter/Timers CLK COUNT = 0002h IOWR (Internal) TCTL2 TOUT2 Count value IOWR ? ? ? COUNT = 0004h 0002h 0001h 0000h FFFFh 0002h 0001h 0002h FFFFh FFFEh 0001h COUNT = 0003h (Internal) TCTL2 TOUT2 Count value ? ? ? 0004h 0003h 0002h 0001h 0000h 0003h Figure 7–12. Mode 5 Operation.
Counter/Timers Programming The TCU is enabled and mapped into an I/O address range using the V40 configuration register. The TCU includes three counter/timers and four programmable registers. The first register to be programmed is the Mode register. This register selects one of the three counter/timers and information needed for initialization. The next register to be programmed is the Count register for the counter/timer being used.
Chapter 8 INTERRUPT CONTROLLER (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller (V40) OVERVIEW This chapter describes the Interrupt Control Unit (ICU) and provides register descriptions. The ICU is a programmable interface between interrupt-generating peripherals and the CPU. The ICU monitors eight interrupt inputs with programmable priority. When peripherals request service, the ICU interrupts the CPU with a pointer to a service routine for the highest priority device.
Interrupt Controller (V40) ZT 8832 SPECIFICS The inputs to the interrupt controller are connected as shown in Table 8-1. Table 8-1 Interrupt Controller Inputs.
Interrupt Controller (V40) FUNCTIONAL DESCRIPTION The format of the ICU programmable registers is the same as the industry standard 8259 Programmable Interrupt Controller, with one exception: 8085 operation is not supported. The ICU can be divided into seven functional blocks as shown in Figure 8-1.
Interrupt Controller (V40) Interrupt Mask Register All interrupt requests are latched by the Interrupt Request register. The Interrupt Mask register acts as a programmable filter to selectively disable requesting interrupts from being serviced. The IMK is an 8-bit register with one bit position for each interrupt input. Setting a bit to a logical 1 prevents the respective interrupt request from being transferred from the Interrupt Request register to the Interrupt In-Service register.
Interrupt Controller (V40) Control Logic This functional block directs the operation of the other ICU blocks based on the programmed mode of operation. The Control Logic also interfaces to the CPU for interrupt request and acknowledge signals. An interrupt request is generated to the CPU if an ICU input has the correct priority and is not masked. If the CPU interrupts have been enabled with the "set interrupt" command, it will respond with an interrupt acknowledge.
Interrupt Controller (V40) PROGRAMMABLE REGISTERS The ICU is initialized with Interrupt Initialization Word 1 (IIW1) through Interrupt Initialization Word 4 (IIW4). Once initialized, the operation of the ICU is controlled with the Interrupt Mask Word (IMKW), Interrupt Priority and Finish Word (IPFW), and Interrupt Mode Word (IMDW). Three status words can also be read to interrogate the operation of the ICU: the Interrupt Request (IRQ), Interrupt In-Service (IISI), and Interrupt Poll (IPOL).
Interrupt Controller (V40) Initialization Words (IIW1, IIW2, IIW3, and IIW4) The ICU must be initialized before it can be used. Initialization consists of writing from two to four bytes called interrupt initialization words. The sequence in which these words are programmed is outlined in the flow chart shown in Figure 8-2. IIW1 and IIW2 must be programmed during any initialization sequence. IIW3 is not supported by the ZT 8832 and should be initialized to zero.
Interrupt Controller (V40) IIW1 and IIW2 Interrupt Initialization Words 1 (IIW1) and 2 (IIW2) are required for ICU initialization. The IIW1 register, shown in Figure 8-3, is divided into two fields labeled II4 (Interrupt Initialization 4) and LEV (Level). The II4 bit selects whether or not the IIW4 register is to be programmed. If II4 is set to a logical 1, the ICU expects IIW4 to be written as part of the initialization.
Interrupt Controller (V40) The ICU responds to an interrupt acknowledge by supplying the CPU with an interrupt vector based on which interrupt generated the request and the value programmed into IIW2. The format for IIW2 is shown in Figure 8-4. Bits V3 through V7 define the upper 5 bits of the vector address. 7 6 5 4 3 2 1 0 V7 V6 V5 V4 V3 — — — IIW2 Address: Base + 1 Access: Write Higher 5 bits of interrupt vector number Figure 8–4. Interrupt Initialization Word 2.
Interrupt Controller (V40) IIW4 Figure 8-6 shows the architecture for IIW4. IIW1 must be programmed with a logical 1 in the II4 bit if IIW4 is used. A logical 1 in the SFI bit enables the Self Finish Interrupt and a logical 0 disables it. The interrupt service routine must include an EOI command when the Self Finish Interrupt is disabled. 7 6 5 4 3 2 1 0 0 0 0 0 — — SFI 1 IIW4 Address: Base + 1 Access: Write Self Finish Interrupt 0 Finish interrupt 1 Self finish interrupt Figure 8–6.
Interrupt Controller (V40) Operation Words (IMKW, IPFW, and IMDW) Once initialized, the operation of the ICU is controlled with three 8-bit values called the Interrupt Mask Word (IMKW), Interrupt Priority and Finish Word (IPFW), and the Interrupt Mode Word (IMDW). The Operation Words can be transferred in any sequence to perform such functions as enabling and disabling individual interrupt requests and changing interrupt priorities. IMKW The IMKW masks interrupt request inputs.
Interrupt Controller (V40) IPFW IPFW selects fixed or rotating priorities and the method of informing the ICU that an interrupt has been serviced. Operation of the ICU can be changed at any time by writing a new IPFW. Refer to Figure 8-8 when programming the IPFW.
Interrupt Controller (V40) The IL0 through IL2 bits designate an interrupt level. This level is used by certain combinations of the FI, SIL, and RP bits either to reset an interrupt request that has been recognized or to set a specific priority. The ICU uses the IIS register to keep track of which interrupts are being serviced and their relative priorities. The ICU updates the IIS register based on a Finish Interrupt command.
Interrupt Controller (V40) IMDW IMDW controls the method of reading status from the ICU and enables a special type of interrupt masking. The format of the IMDW is shown in Figure 8-9. The first two bits are used to select the IRQ and IIS registers so they can be read by the application software. A logical 1 in bit 0 selects the IIS register and a logical 0 selects the IRQ register. A logical 1 in the SR bit (bit 1) enables the reading of the IRQ and IIS registers.
Interrupt Controller (V40) The POL bit selects the poll command. The two most commonly used methods of servicing peripherals in a microprocessor system are polling and interrupts. Although interrupts are the fastest method of servicing peripherals, using the ICU in a polled operation is still faster than polling each peripheral one at a time. Setting the POL bit to a logical 1 enables the reading of the poll status. The POL bit overrides the SR bit if both are set.
Interrupt Controller (V40) IRQ and IIS The IRQ and IIS status words, shown in Figure 8-10 below, are taken directly from the Interrupt Request register and Interrupt InService register, respectively. The IRQ status word contains all the interrupt levels requesting service. The IIS status word contains all the interrupt levels currently being serviced. Bit 0 of both status words corresponds to IRQ0, bit 1 corresponds to IRQ1, and so on.
Interrupt Controller (V40) Figure 8-11 shows the IPOL status word. Bits PL0 through PL2 define the highest priority interrupt input requesting service. For example, if all three bits are set to a logical 1, then IRQ7 is the highest priority request. The INT bit (bit 7) indicates whether there are any interrupt requests. A logical 1 signals an interrupt request and a logical 0 signals no interrupt request. If INT is a logical 0, PL0 through PL2 are all set to a logical 1.
Interrupt Controller (V40) OPERATION Reset The ICU registers are not initialized to a default state when power is applied to the ZT 8832 or after a reset. The OPCN V40 configuration register is initialized to disable the ICU, which disables interrupts. Interrupts Most microprocessor systems include peripheral devices designed to perform specific tasks. Examples include counter/timers, serial controllers, and real-time clocks.
Interrupt Controller (V40) The V40 interrupt acknowledge cycle is two machine cycles long and looks much the same as two I/O read cycles. The difference is that the CPU interrupt acknowledge signal is pulsed low for two clock periods each machine cycle instead of the read signal. The first interrupt acknowledge pulse prepares the ICU to provide an interrupt vector on the second. Preparation includes freezing the state of the interrupts internal to the ICU so the highest priority request can be determined.
Interrupt Controller (V40) Interrupt Vectors The CPU responds to all external interrupt requests by reading an 8-bit value from the interrupt device that indirectly points to the subroutine used to service the device. The 8-bit value is called the interrupt vector and the subroutine used to service the device is the interrupt service routine. The relationship between the interrupt vector provided by the ICU and the address of the interrupt service routine is illustrated in Figure 8-12.
Interrupt Controller (V40) Interrupt Nesting Interrupt nesting is a powerful structure that allows an interrupt currently under service to be suspended while a second interrupt is serviced. The ICU supports nested interrupts. In most cases, the second interrupt must be a higher priority than the one currently being serviced. The exceptions to the rule are listed below.
Interrupt Controller (V40) Main Program SI IRQ3 Interrupt ... IRQ3 Service Routine IRQ1 Interrupt SI IRQ1 Service Routine ... FI FI RET RET Figure 8–13. Nested Interrupt Structure.
Interrupt Controller (V40) Next, an IRQ1 request occurs. Since interrupts are automatically disabled upon entering a service routine, the IRQ1 request is not acknowledged until the "set interrupt" command is executed. Note that if a lower priority input such as IRQ4 generates a request, it will not be serviced until all higher priority requests are serviced. The CPU vectors program execution to the IRQ1 service routine. At this point in the sequence, the IIS register has bits IRQ3 and IRQ1 set.
Interrupt Controller (V40) Level- or Edge-Triggered The two primary methods of sensing interrupt requests are to sense the logical state (level) or the transition between logical states (edge) of the interrupt request inputs. The ICU is programmed for level- or edge-triggered interrupt sensing with the IIW1 register. Level-Triggered Sensing If programmed for level-triggered mode, the ICU recognizes a logical 1 as an interrupt request.
Interrupt Controller (V40) Finish Interrupts The ICU must be told when a service routine is completed so that the in-service bit of the IIS register can be cleared. The three finish interrupt formats that the ICU recognizes are the nonspecific finish interrupt, specific finish interrupt, and automatic finish interrupt. Nonspecific FI The ICU accepts a nonspecific FI as an indication of interrupt service completion of the highest priority request.
Interrupt Controller (V40) Automatic Finish Interrupt When programmed for automatic FI, the ICU automatically executes a nonspecific FI during the interrupt acknowledge cycle. The advantage of the finish interrupt format is that you need no longer issue a command to the ICU that a service routine is completed. Like the nonspecific FI, the automatic FI must be used only in operating modes in which the service routine of the highest priority request is the first one completed.
Interrupt Controller (V40) Automatic Priority Rotation Automatic priority rotation is used in applications with interrupt devices that are of equal priority. In this mode of operation, after an interrupt request is serviced the ICU rotates it into the lowest priority slot. This guarantees that all interrupt requests will be serviced. The nonspecific FI or specific FI commands can be used for automatic priority rotation.
Interrupt Controller (V40) Specific Priority Rotation Specific rotation, like automatic rotation, can be used to change the priorities of the ICU inputs. With automatic rotation, the last request serviced is rotated into the lowest priority, and other ICU inputs are rotated up one level. With specific rotation, you specify which interrupt receives the lowest or highest priority. Either the set priority command or the rotate on specific FI command can be used to select this operating mode.
Interrupt Controller (V40) Interrupt Masking The ICU inputs are all maskable. The "clear interrupt" instruction can be executed to disable all ICU inputs from generating interrupts. In certain applications it may be necessary to disable, or mask, selected ICU inputs. The ICU Interrupt Mask register (IMKW) includes one bit for each ICU input to permit selective masking. An interrupt, masked or not, flags a request by setting a bit in the IRQ register.
Interrupt Controller (V40) Interrupt Status The Interrupt Request (IRQ), Interrupt In-Service (IIS), and Interrupt Mask (IMKW) registers are available to the programmer. The IRQ and IIS registers are read by first writing the appropriate read register command to the ICU IMDW register. After the read register command is written, the selected register can be read any number of times.
Chapter 9 DMA CONTROLLER (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Internal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Address Register . . . . .
DMA Controller (V40) OVERVIEW This chapter describes the Direct Memory Access Control Unit (DCU) and provides register descriptions. The DCU is a programmable peripheral device used to direct high speed data transfers between the ZT 8832 and SBX expansion module I/O. The approximate data rate between the expansion module and local RAM using standard input and output instructions is 235 Kbytes per second. Using DMA, the data transfer rate is increased to approximately 1.
DMA Controller (V40) ZT 8832 SPECIFICS The ZT 8832 uses one of the four DMA controllers contained in the V40. DMA channel 0 is used to coordinate high speed data transfers between the SBX expansion module I/O and local or dual port memory. The SBX expansion module must support DMA by driving Expansion Module DMA Request (MDRQT) on J4 pin 34 and receiving Expansion Module DMA Acknowledge (MDAK) on J4 pin 32. The DMA interface does not support Terminate DMA (TDMA) on J4 pin 26.
DMA Controller (V40) FUNCTIONAL DESCRIPTION Figure 9-1 illustrates a block diagram of the DCU. The DCU is divided into six major blocks for explanation purposes. Each of these functional blocks is discussed below. Address Adjuster A0-A19 D0-D15 CONTROL Internal Bus Interface Current Address Control Registers Base Address Initialization Address Register BRQ BAK DRQ DAK Channel Status Mask Device Control Mode Control Count Register Current Count Base Count Count Adjuster Figure 9–1.
DMA Controller (V40) Internal Bus Interface The Internal Bus Interface monitors address and data buses for programming information. The Internal Bus Interface also generates Bus Request (BRQ) to request access to the address, data, and control buses in response to a DMA Request (DRQ) from the SBX expansion module. The CPU acknowledges BRQ with Bus Acknowledge (BAK), signaling the Internal Bus Interface to generate DMA Acknowledge (DAK) to the SBX expansion module and perform the data transfer.
DMA Controller (V40) Count Register The Count register includes a 16-bit base count and a 16-bit current count. The base count and current count are programmed with the number of bytes to be transferred by the DMA operation. The base count remains the same until a new count is specified. If the autoinitialize feature is used, the base count is transferred to the current count when the count register is decremented to zero and the last DMA operation is complete.
DMA Controller (V40) PROGRAMMABLE REGISTERS The DCU occupies 16 consecutive I/O port addresses. Of those 16 addresses, 12 are used by the programmer to access DCU functions and 4 are reserved. Table 9-1 lists the address of each of the registers relative to a programmable base address. The base address is selected with the OPHA and DULA V40 configuration registers; see page 6-5 for details. Table 9-1 DCU Register Addressing.
DMA Controller (V40) DMA Initialize Command (DICM) The initialization command, shown in Figure 9-2, includes one bit that can be set to a logical 1 to reset the DCU. This register must be written to with the byte output instruction. 7 6 5 4 3 2 1 0 — — — — — — 0 RES Register:DICM Address:Base + 0 Access:Write Only Reset 0 No reset 1 Reset Figure 9–2. DMA Initialization Command Register.
DMA Controller (V40) For read operations, the BASE bit set to a logical 0 defines whether the current register is made available for a read operation or whether the base and current registers are written to during a write operation. A logical 1 in the BASE bit means the base register is selected.
DMA Controller (V40) DMA Base Count/Current Count (DBC/DCC) Two DBC/DCC registers make up the 16-bit DMA count, as shown in Figure 9-4. The two DBC/DCC registers can be accessed with byte or word instructions. The function of these registers depends on the BASE bit of the DCH register. If the BASE bit is set to a logical 0, the values written to the Count registers are programmed into both base and current count values.
DMA Controller (V40) DMA Base Address/Current Address (DBA/DCA) Three DBA/DCA registers specify the 20-bit address. The format of these registers is shown in Figure 9-5. The lower 16 bits of the address can be accessed with byte or word instructions. The upper four bits must be accessed with byte instructions. As is the case with the DBC/DCC registers, the BASE bit of the DCH register defines the operation of the DBA/DCA registers.
DMA Controller (V40) DMA Device Control (DDC) Two DDC registers select various DCU operating modes. The format for these registers is shown in Figure 9-6. These registers can be accessed with byte or word operations. The DDMA bit can be set to a logical 1 to prevent the DCU from requesting bus access. This should be done when programming any of the DCU registers to prevent incorrect DMA operation, The WEV bit enables or disables wait states to be inserted by the V40 WCU during the verify operation.
DMA Controller (V40) DMA Mode (DMD) Figure 9-7 shows the format of the DMD register. The DMD register can be accessed with byte or word instructions. The TDIR field defines the mode of data transfer. A logical 0 in both bits selects the verify operation. A logical 1 in bit 2 and a logical 0 in bit 3 selects I/O-to-memory transfers. For memory-to-I/O transfers, bit 2 must be programmed with a logical 0 and bit 3 with a logical 1.
DMA Controller (V40) Autoinitialize is a feature that automatically reloads the DCU Current Address and Current Count registers from the Base Address and Base Count registers, respectively. The reload is done when the Count register reaches zero. The autoinitialize feature is disabled by programming AUTI with a logical 0 and enabled with a logical 1. The ADIR bit defines the operation of the DCU address adjuster.
DMA Controller (V40) DMA Status (DST) The Status register includes information about the currently programmed state of the DMA channel. The format for DST is shown in Figure 9-8. DST is accessed with the byte read instruction. The TC0 bit indicates when the count register has reached zero and the DMA transfer is completed. A logical 0 in TC0 means that the operation has not been terminated and a logical 1 means that it has. The RQ0 bit defines the state of the DMA request input.
DMA Controller (V40) DMA Mask (DMK) The DMK register, shown in Figure 9-9, is used to mask DMA requests made by the DMA channel. The register is accessed with either byte write or read instructions. To mask a DMA channel, the respective bit must be programmed with a logical 1. A logical 0 enables the DMA channel to make requests. 7 6 5 4 3 2 1 0 — — — — 1 1 1 M0 Register:DMK Address:Base + F Access:Read or Write DMARQ Mask 0 Not masked 1 Masked Figure 9–9. DMA Mask Register.
DMA Controller (V40) OPERATION Reset The DCU registers are initialized after power-on or after a pushbutton reset. Table 9-2 shows the initialized state. Table 9-2 DCU Register Default State. Default Bit Value [1] Register 7 6 5 4 3 2 1 0 DCH DMD DDC (low) DDC (high) DST DMK 0 - 0 - 0 0 - 0 0 0 - 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 [1]Bit positions marked with a dash (-) can default to 1 or 0.
DMA Controller (V40) Block Mode Transfers In block transfer mode, the DCU continues servicing the DMA channel until the count register is decremented to zero. At this time the DCU releases control of the buses and enters a slave mode of operation, permitting lower priority bus masters to gain access to the bus resources. Autoinitialization Autoinitialization is useful when doing repetitive DMA transfers using the same amount of data and the same memory locations.
Chapter 10 SERIAL COMMUNICATIONS (V40) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Receiver . . . . . . .
Serial Communications (V40) OVERVIEW This chapter describes the Serial Control Unit (SCU) and provides register descriptions and baud rate information. The SCU is a single serial channel that performs asynchronous serial communication between the V40 and a serial device external to the ZT 8832. The major features of the SCU are listed below. • Full-duplex asynchronous operation • Clock divisor of 16 or 64 • Baud rates to 38.
Serial Communications (V40) FUNCTIONAL DESCRIPTION The SCU is similar to the 8251 Serial Control Unit for asynchronous operation. The SCU does not support synchronous communication protocols. Figure 10-1 shows a functional block diagram of the SCU. A description of each functional block follows.
Serial Communications (V40) Read/Write Control The Read/Write Control block acts as an interface between the internal registers of the SCU and the CPU. The control signals input to the Read/Write Control logic, select internal registers, and control the transfer of information between the CPU and the SCU. Receiver The Receiver block converts serial data input on the RxD signal to a parallel format with the start, stop, and parity bits removed.
Serial Communications (V40) PROGRAMMABLE REGISTERS Six registers are used for communication with the SCU. The Serial Transmit Buffer (STB) and Serial Receive Buffer (SRB) store data to be transferred to the serial link and from the serial link, respectively. The Serial Command (SCM) and Serial Mode (SMD) registers define the operating mode. The Serial Interrupt Mask (SIMK) register controls the receive and transmit interrupts.
Serial Communications (V40) Serial Status Register (SST) Figure 10-2 shows the architecture of the SST register, which can be read at any time.
Serial Communications (V40) Buffer Ready) bit is set to a logical 1 when a character is transferred into the SRB. Application software uses RBRDY to determine if a character is available. RBRDY is automatically reset when the character is read from the SRB. The PE (Parity Error), OVE (Overrun Error) and FE (Framing Error) bits flag data communication errors. The PE bit is set to a logical 1 if a character is received into the SRB with a mismatch between the parity bit and the character itself.
Serial Communications (V40) Serial Command Register (SCM) Figure 10-3 illustrates the SCM register bit map. The SCU is configured with the SCM and the SMD registers. The SCM register includes the functions that are most likely to be modified during operation. The SMD register will more than likely be programmed just once for initialization.
Serial Communications (V40) error conditions occur and remain set until a logical 1 is written to the ECL bit. Serial Mode Register (SMD) Figure 10-4 shows the format for the SMD register. This register includes all the functions that are not likely to change after they have been initialized. Bits 1 and 2 combine to define the clock divisor for the baud rate. Programming the baud rate is defined in more detail on page 10-13. The character length is programmed with the CL field.
Serial Communications (V40) Enabling even or odd parity is the function of the PS field. Parity is disabled if a logical 0 is written to bit 4. If parity is disabled, the parity bit will not be appended to the characters transmitted and the characters received will not be tested. If bit 4 is a logical 1, parity is enabled. Bit 5 selects between even or odd format. A character has even parity if it includes an even number of bits set to a logical 1.
Serial Communications (V40) OPERATION Reset The SCU registers are automatically initialized to a default state when power is applied to the ZT 8832, or during a reset. Table 10-2 shows the default state for these registers. Table 10-2 SCU Register Defaults. Register 7 Default Bit Value [1] 6 5 4 3 2 SST SCM SMD SIMK 1 0 - 0 1 - 0 0 0 - 0 0 0 - 0 0 1 - 1 0 0 - 1 0 0 1 1 0 0 1 1 [1] Bit positions marked with a dash (-) can default to 1 or 0.
Serial Communications (V40) Serial Data Format The SCU supports asynchronous communication. The asynchronous data format is shown in Figure 10-6 to include start, stop, and optional parity bits, as well as seven or eight data bits. The state of the TxD line, when data is not being transmitted, is the "mark" state. The start bit indicates the beginning of the serial data or character bits. The parity bit is inserted for transmission and tested for reception if parity is enabled in the SMD register.
Serial Communications (V40) Baud Rate The SCU baud rate is determined by the output of counter/timer 1. Counter/timer 1 must be initialized for a specific mode of operation and programmed with a count that defines the required baud rate. The discussion below explains initialization and how to calculate the count. To use counter/timer 1 as a baud rate generator, the TCKS register ust specify that counter/timer 1 has an internal clock with a divisor determined by the formula shown below.
Serial Communications (V40) The calculation to determine the count value to be programmed into counter/timer 1 is shown below to be 26. Note that the calculated count and the programmed count differ by 0.16 percent. To guarantee proper operation, the percent difference must never be greater than four. Table 10-3 lists the count values to be programmed into counter/timer 1 to generate the more common baud rates. Count = 8 x 106 / (2 x 9600 x 16) = 26.04 Table 10-3 ZT 8832 Baud Rate Counts.
Serial Communications (V40) If the counter/timers are driven with the external TCLK pin through connector J3, instead of with the V40 clock, use the formula below for calculating the value to be loaded into counter/timer 1. Note that the frequency of the external clock signal is not dependent on the PS bit of the TCKS register. Count = External Clock / (Baud Rate x Baud Factor) Interrupt and Polled Communication Serial data can be transferred and received either by polling status bits or with interrupts.
Serial Communications (V40) Programming The SCU is enabled and mapped into an I/O address range using the V40 Configuration register. The SCU includes four programmable registers. The steps listed below outline the procedure for programming the SCU for serial operation. The steps include initializing counter/timer 1 to generate the baud rate. 1. Program the TCKS V40 configuration register for counter/timer 1 to use the internal clock divided by two.
Chapter 11 SERIAL COMMUNICATIONS (82050) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Receiver . . . . . .
Serial Communications (82050) OVERVIEW This chapter describes the Asynchronous Communication Controller (ACC) and provides register descriptions and baud rate information. The ACC is the Intel 82050 or equivalent. It is a single asynchronous serial channel that performs serial communication between the ZT 8832 and an external serial device. The major features of the ACC are listed below.
Serial Communications (82050) ZT 8832 SPECIFICS The ACC serial port, available at connector J2, includes Transmit Data (TxD), Receive Data (RxD), and support for a complete selection of the following modem control functions: • Clear To Send (CTS) • Request To Send (RTS) • Data Terminal Ready (DTR) • Data Set Ready (DSR) • Ring Indicator (RI) • Data Carrier Detect (DCD) The serial port is jumper configured to operate as either Data Communication Equipment (DCE) or Data Terminal Equipment (DTE) w
Serial Communications (82050) FUNCTIONAL DESCRIPTION The ACC is functionally compatible with the industry standard 16450/8250A found in most Personal Computers. Figure 11-1 illustrates the major functional blocks of the ACC. A description of each functional block follows.
Serial Communications (82050) Read/Write Control The main function of the Read/Write Control block is to supervise the interface between the ACC internal registers and the CPU. This includes enabling one of the ACC programmable registers onto the system data bus based on control signal inputs. Receiver The Receiver block converts serial data input on the RxD signal to a parallel format with the start, stop, and parity bits removed.
Serial Communications (82050) Modem Control The Modem Control block includes the serial communication handshake, RS-485 buffer control, and parallel port enable signals. The serial handshake signals output by this control block are Request to Send (RTS) and Data Terminal Ready (DTR). The DTR signal also serves as an enable for the Transmit Data and Request To Send drivers when the ACC is configured for RS-485 operation. Both the RTS and DTR signals are programmable through the Modem Control register.
Serial Communications (82050) PROGRAMMABLE REGISTERS The remainder of the functional blocks illustrated in Figure 11-1 are programmable registers. Table 11-1 shows the address of each of the registers. Table 11-5 on pages 11-25 and 11-26 summarizes the ACC register set for programming reference. Table 11-1 ACC Register Addressing.
Serial Communications (82050) Transmit and Receive Buffer The Transmit Buffer, Receive Buffer, and Interrupt Enable registers share the same addresses as the Divisor Latch. Since the Divisor Latch is programmed only once during system initialization, this should cause no problems. During system initialization, the Divisor Latch is selected by programming the Divisor Latch Access Bit of the Line Control register.
Serial Communications (82050) 7 6 DLAB SB 5 SP 4 3 2 EPS PEN STB 1 0 WLS Register:Line Control Address:03FBh Access:Read/Write Word Length Select 00 5 bits 01 6 bits 10 7 bits 11 8 bits Stop Bits 0 1 stop bit 1 2 stop bits (1-1/2 if WLS = 00) Parity Enable 0 No parity 1 Parity Even Parity Select 0 Odd Parity 1 Even Parity Stick Parity 0 Disabled 1 Enabled Set Break 0 Disabled 1 Enabled Divisor Latch Access 0 Disabled 1 Enabled Figure 11–2. Line Control Register.
Serial Communications (82050) The STB bit selects the number of stop bits added to each character transmitted and removed from each character received. Programming STB with a logical 0 selects one stop bit; a logical 1 selects two stop bits. The exception to this is when the character length is defined as five. In this case, a logical 1 selects one and a half stop bits. The parity options are programmed through the PEN, EPS, and SP bits. PEN (bit 3) enables and disables parity.
Serial Communications (82050) Line Status The Line Status register, shown in Figure 11-3, provides information to the CPU concerning the data transfer. Reading the Line Status register clears bits 1 through 4 (OE, PE, FE, and BI).
Serial Communications (82050) The DR bit indicates the state of the ACC Receive Buffer. A logical 1 in the DR bit signals the availability of a character in the Receive Buffer. The DR bit is automatically reset to a logical 0 when the Receive Buffer is read. The OE, PE, and FE bits are transmission error indicators. An overrun error is indicated by a logical 1 in the OE bit, a parity error is indicated by a logical 1 in the PE bit, and a framing error is indicated by a logical 1 in the FE bit.
Serial Communications (82050) Modem Control The Modem Control register, shown in Figure 11-4, includes the serial handshake, RS-485 driver enable, and parallel port enable signals. 7 6 5 0 0 0 4 3 LOOP OUT2 2 0 1 0 RTS DTR Register:Modem Control Address:03FCh Access:Read/Write Data Terminal Ready 0 DTR = mark 1 DTR = space Request To Send 0 RTS = space 1 RTS = mark Output 2 0 Parallel ports disabled 1 Parallel ports enabled Loopback Diagnostics 0 Disabled 1 Enabled Figure 11–4.
Serial Communications (82050) The RTS bit (bit 1) defines the state of the Request To Send (RTS) signal. Programming the RTS bit with a logical 0 forces RTS to a marking (negative) state, and programming the RTS bit with a logical 1 forces RTS to a spacing (positive) state. Bit 2 is permanently set to logical 0. The OUT2 bit (bit 3) defines the state of the Output 2 (OUT2) signal. The OUT2 signal is connected to the output control of the three parallel ports available at connector J1.
Serial Communications (82050) Modem Status Figure 11-5 shows the format of the Modem Status register. All eight bits of this register are used to indicate the status of the serial data transfer.
Serial Communications (82050) The DCTS, DDSR, and DDCD bits (bits 0, 1, and 3) are set to a logical 1 to indicate that the CTS, DSR, and DCD bits have changed state since the last time the Modem Status register was read. The TERI bit (bit 2) signals the trailing edge detection of the Ring Indicator (RI). The TERI bit is a logical 1 if the RI input changed from a spacing (positive) state to a marking (negative) state since the last time the Modem Status register was read.
Serial Communications (82050) Divisor Latch The ACC baud rate is selected by programming the least significant byte (LSB) and most significant byte (MSB) of the Divisor Latch shown in Figure 11-6. The Divisor Latch is programmed with an integer value that divides the ACC oscillator reference frequency of 18.432 MHz into a value of 16 times the baud rate for both transmission and reception of serial data. The most common baud rate divisors are shown in Table 11-4 on page 11-22.
Serial Communications (82050) Interrupt Identify The ACC includes 10 sources of interrupts prioritized into four categories. The Interrupt Identify register flags whether or not the ACC has an interrupt pending and, if so, from which of the four categories it originated. Figure 11-7 below shows the format for the Interrupt Identify register. The IP bit indicates whether an interrupt is pending. A logical 0 in IP signals an active interrupt, and a logical 1 in IP signals no active interrupt.
Serial Communications (82050) Interrupt Enable The Interrupt Enable register, shown in Figure 11-8, defines which of the four categories of interrupts are enabled and which are not. The Interrupt Enable register includes one bit for each of the four categories of interrupts. Setting bits 0 through 3 all to a logical 0 prevents the ACC from generating an interrupt of any kind and inhibits the Interrupt Identify register.
Serial Communications (82050) OPERATION Reset The ACC registers are automatically initialized to a default state after reset. Table 11-3 shows the default state for these registers. Table 11-3 ACC Register Defaults.
Serial Communications (82050) Serial Data Format The ACC supports asynchronous data transfers. The format for the asynchronous data includes start, stop, and optional parity bits as well as five, six, seven, or eight data bits. This is illustrated in Figure 11-9. Marking Start Bit 7 or 8 Data Bits Optional Parity Bit Asynchronous Data Format Marking Start Bit 7 or 8 Data Bits 1 or 2 Stop Bits Optional 1 or 2 Stop Parity Bits Bit Break Sequence Format Figure 11–9. ACC Serial Data Format.
Serial Communications (82050) Baud Rate The ACC includes an internal baud rate generator to divide the 18.432 MHz reference frequency down to a value equal to 16 times the baud rate. The divisor for the reference frequency is a 16-bit integer programmed into the LSB and MSB of the Divisor Latch. The relationship between the baud rate and the count is as follows: 6 Divisor = 18.432 x 10 /(160 x Baud Rate) Table 11-4 lists the divisor to be used for the more popular baud rates.
Serial Communications (82050) Interrupt and Polled Communication Serial data can be transferred and received either by polling status bits or with interrupts. In a polled mode, the application program monitors the Line Status register Data Ready and Transmitter Holding Register Empty bits to determine when to transfer a character to the ACC or when a character is available. The ACC is capable of generating interrupts for applications that cannot afford time wasted in polling for a status change.
Serial Communications (82050) Appendix B includes the pin numbers and signal descriptions of the RS-232-C and RS-485 signals available through connector J2. (See page B-13.) When configured for RS-485, Data Terminal Equipment (DTE) is selected by plugging in the serial cable with pin 1 of the cable lined up with pin 1 of the connector. To select Data Communication Equipment (DCE), the serial cable should be plugged in with pin 1 of the cable lined up with pin 14 of the connector.
Serial Communications (82050) Table 11-5 ACC Register Summary. Register Address 0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 3 Bit Interrupt IdenNo.
Serial Communications (82050) Table 11-5 ACC Register Summary (continued).
Chapter 12 PARALLEL I/O Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O ZT 8832 SPECIFICS The three parallel ports are available at connector J1; see page B-11 for pin assignments. In addition to the 24 I/O signals, connector J1 also supports ground and fused +5 V for direct interface to industry standard I/O module mounting racks, such as Ziatech’s ZT 2226 or those manufactured by Opto 22. The 1 A fuse is available from Littelfuse (part number 275-001). The two most significant parallel port signals are connected to other devices in addition to the J1 connector.
Parallel I/O FUNCTIONAL DESCRIPTION A functional diagram of each of the 24 I/O signals is illustrated in Figure 12-1. The diagram includes an Output Latch, an Output Buffer, and an Input Buffer. These functional blocks are described below. Output Latch The Output Latch stores the data present on the internal data bus during a write operation to the parallel port. The data is latched until altered by another parallel port write or until power is turned off.
Parallel I/O Output Buffer The Output Buffer isolates the Output Latch from connector J1. The Output Buffer is disabled and enabled with the 82050 Serial Port OUT2 bit. The OUT2 connection ensures that the Output Buffer is disabled during and after power-up to prevent the I/O signals at connector J1 from glitching. The OUT2 signal also disables the Output Buffer during and after a reset. The Output Buffer is an inverting open collector device.
Parallel I/O PROGRAMMABLE REGISTERS The 24 parallel I/O signals are accessible through three programmable registers. The address of each of the registers is shown in Table 12-1. Table 12-1 Parallel I/O Register Addressing.
Parallel I/O OPERATION Reset The parallel port outputs are disabled and passively pulled to a TTL high after power up or reset. Programming the Parallel Ports The parallel ports are enabled by writing a logical 1 to the 82050 serial port OUT2 bit (I/O port address 3FCh, bit 3). This operation immediately transfers the contents of the parallel ports to the J1 connector. The contents of the parallel ports are not defined after power-up.
Parallel I/O Programming the Light Emitting Diode • To control the LED, first enable the parallel port by programming the OUT2 bit of the 82050 serial port (I/O port address 3FCh, bit 3) with a logical 1. • To turn on the LED, write a logical 1 to the second most significant parallel I/O bit (I/O port address 220h, bit 6). • To turn off the LED, write a logical 0 to the second most significant parallel I/O bit (I/O port address 220h, bit 6).
Chapter 13 WATCHDOG TIMER Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stage 1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stage 1 Delay . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer OVERVIEW The primary function of the watchdog timer is to monitor ZT 8832 operation and to take corrective action if the ZT 8832 fails to function as programmed. The watchdog timer includes two stages. The firststage timeout generates a non-maskable interrupt. The second-stage timeout generates a local reset. The major features of the watchdog timer are listed below.
Watchdog Timer FUNCTIONAL DESCRIPTION Figure 13-1 illustrates a functional diagram of the watchdog timer. The diagram includes a timer and a delay for each stage. The functional blocks are described below. Stage 1 Timer The first stage of the watchdog timer generates a non-maskable interrupt to the local CPU if the watchdog timer is jumper selected and armed and a strobe does not occur within the time period defined by the Stage 1 Delay functional block.
Watchdog Timer Stage 1 Delay The stage 1 delay has a default range of 60 ms minimum and 100 ms maximum. The minimum delay time means that the watchdog timer must be strobed with a period of less than 60 ms to prevent stage 1 from generating a non-maskable interrupt. The maximum delay time means that it could take up to 100 ms after the watchdog timer is strobed before the non-maskable interrupt occurs.
Watchdog Timer OPERATION In operation, the local CPU is programmed to strobe the watchdog timer at a periodic rate less than the stage 1 time delay. If the local CPU fails to operate as programmed, stage 1 of the watchdog timer generates a non-maskable interrupt. The non-maskable interrupt service routine takes the necessary corrective action that includes strobing the watchdog timer before the stage 2 time delay to prevent a local reset.
Watchdog Timer Multiple Stages Many watchdog timers are implemented with a single stage that generates a reset if allowed to time out. The problem with this implementation is that the CPU does not have advance warning of the reset. Without advance warning, the CPU cannot take corrective action that includes, as a minimum, setting a flag indicating that a system failure has occurred. Other watchdog timers are implemented with a single stage that generates a non-maskable interrupt if allowed to time out.
Watchdog Timer Changing Time Delays Table 13-1 shows the two possibilities for the stage delays. The stage 1 delay is measured from the watchdog strobe to the nonmaskable interrupt. The stage 2 delay is measured from the watchdog strobe to the local reset. The stage 2 - stage 1 delay is calculated as the non-maskable interrupt to local reset delay. The first entry in Table 13-1 shows the default stage delays. The second entry shows an option.
Watchdog Timer Programming The watchdog timer is armed and strobed with the most significant parallel I/O signal. The watchdog timer is armed with the following programming sequence. 1. Initialize the most significant bit of the parallel ports (I/O port address 220h, bit 7) with a logical 0. 2. Enable the parallel ports by writing a logical 1 to the 82050 OUT2 bit (I/O port address 3FCh, bit 3). 3. Arm the watchdog timer by programming the most significant bit of the parallel ports with a logical 1.
Chapter 14 SBX EXPANSION MODULE Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBX Expansion Module OVERVIEW The SBX expansion module provides a method for expanding the I/O capabilities of the ZT 8832. The expansion module interface is electrically, mechanically, and functionally compatible with the Intel iSBX MULTIMODULE standard. This level of compatibility ensures that expansion modules produced by other manufacturers will operate with the ZT 8832.
SBX Expansion Module Features The major features of the expansion module interface are listed below.
SBX Expansion Module ZT 8832 SPECIFICS The expansion module interface is supported through connector J4; the pin assignments given on page B-15. The expansion module supports Direct Memory Access (DMA) using the DMA controller discussed in Chapter 9. The DMA controller transfers data between the expansion module and either local or dual port RAM at rates of up to 1 1/3 Mbytes per second. The DMA signals supported are DMA Request (MDRQT) and DMA Acknowledge (MDACK*).
SBX Expansion Module INSTALLATION The SBX expansion module is installed on the ZT 8832 as shown in Figure 14-1. The module is mechanically secured to the ZT 8832 at the J4 connector and with the threaded spacer shipped with the expansion module. Figure 14–1. SBX Expansion Module Installation.
Chapter 15 NUMERIC DATA PROCESSOR (8087) Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 SPECIFICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numeric Data Processor (8087) OVERVIEW The V40 is a high performance microprocessor designed for a wide variety of applications. The math capabilities of the V40 include addition, subtraction, multiplication, and division of 8-bit and 16-bit numbers. However, the STD bus is often used in numerically intensive applications needing more powerful arithmetic operations and data types than those provided by the V40. The addition of the 8087 Numeric Data Processor (NDP) will provide the following benefits.
Numeric Data Processor (8087) INSTALLATION INSTALL 8087 HERE ZT 8832 ICP The NDP is installed in an empty socket on the ZT 8832 as shown in Figure 15-1. The 8087-1 (10 MHz) is required for proper operation. Be sure power is not applied to the ZT 8832 during installation. Figure 15–1. 8087 Numeric Data Processor Installation.
Numeric Data Processor (8087) OPERATION The following description is an overview of NDP operation. See the reference section at the end of this chapter for sources with more detailed explanations. Coprocessor Interface Instruction Level Support The purpose of the NDP is to extend the math capabilities of the V40.
Numeric Data Processor (8087) Read and Write Operations If a read operation is required, the NDP latches the address and operand as it appears. If the operand is more than one word long, the NDP is granted access to the address, data, and control buses for subsequent read operations. This means that although the NDP does not have the capability of determining the operand starting address, it can latch the starting address and increment it for subsequent operations.
Numeric Data Processor (8087) Error Handling and Interrupts A numeric error occurs if an operation is attempted with invalid operands or if the result of a computation cannot be accurately represented. Six defined error conditions can occur during the execution of a numeric instruction: • Invalid operation • Overflow • Zero divisor • Underflow • Denormalized operand • Inexact result The NDP can be programmed to interrupt the V40 during any or all of these errors.
Numeric Data Processor (8087) Further Reference – Cooner, Jerome, "An Implementation Guide to a Proposed Standard for Floating Point," Computer, Institute of Electrical and Electronic Engineers, Jan. 1980. – Palmer, John, & Wymore, Charles, "Making Mainframe Mathematics Accessible to MicroComputers," Electronics, 8 May 1982. (or AR-135 from Intel Corporation) – Rash, Bill, "Getting Started with the Numeric Data Processor," Intel Corporation.
IV. APPENDICES JUMPER CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 CUSTOMER SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A JUMPER CONFIGURATIONS Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 JUMPER OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 CUTTABLE TRACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jumper Configurations JUMPER OPTIONS Table A-1 below lists the jumpers associated with each option. It also indicates the pages on which descriptions of these jumpers can be found. Table A-2 beginning on page A-3 describes each jumper option in detail. A dagger (†) in Table A-2 indicates a standard default jumper configuration. Figure A-1 on page A-14 shows the factory default jumper configuration. Figure A-2 on page A-15 provides a blank layout to document your custom jumper configuration.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions. JUMPER # DESCRIPTION W1-W6 J2 DCE/DTE Selection - configures the 82050 serial port for RS-232 Data Terminal Equipment (DTE) or Data Communication Equipment (DCE). See also W9-W18 (page A-4). Remove W1-W6 for RS-485 operation. † DTE W1 DCE W1 W2 W2 W3 W3 W4 W4 W5 W5 W6 W6 †Factory default jumper configuration.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W7, W8 Battery Backup Device Selection - determines whether the local RAM devices, RAM LOW and RAM HIGH, are powered by the battery when the system power is turned off. Note that this operation is valid only if the optional battery is present. The RAM devices must be designed for low power operation (less than 15 µA data retention current).
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W16, W17 J2 RS-485 Output Enable - selects the method of enabling the RS-485 Transmit Data and Request-To-Send drivers. With W16 installed, the drivers are disabled. With both W16 and W17 removed, the drivers are always enabled. With W17 installed, the drivers are enabled with the DTR bit of the serial port (I/O port address 3FCh, bit 0).
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W20 Numeric Data Processor Interrupt - enables the Numeric Data Processor (NDP) to generate a non-maskable interrupt in response to an exception error. This jumper must not be installed if the optional NDP is unplugged.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W23-W25 ROM Device Type - configures the ROM socket for a selected device type. The ROM address range is fixed from 88000h through FFFFFh (480 Kbytes). The 8K, 16K, 32K, 64K, 128K, and 256K devices are redundantly mapped into this address range, and only 480K of the 512K device is used.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W28-W32 STD Bus Dual Port RAM Addressing (20-bit) - defines the address range of the dual port memory as seen by the STD bus CPU. These jumpers map the ZT 8832 dual port RAM into any contiguous 32 Kbyte block within the 1 Mbyte address range for an STD bus supporting 20 address lines. The table on page A-9 shows the address range of the dual port memory for each jumper combination.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued).
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W33-W36 STD Bus Dual Port RAM Addressing (24-bit) - defines the address range of the dual port memory as seen by the STD bus CPU. These jumpers, along with W28-W32, map the ZT 8832 dual port RAM into any contiguous 32 Kbyte block in the 16 Mbyte address range for an STD bus supporting 24 address lines. Install cuttable trace CT14 (see page A-20) to select addressing in the upper 8 Mbytes.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W37-W40 STD Bus I/O Port Addressing - defines the address range of the 16 contiguous I/O ports as seen by the STD bus CPU.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W41-W43 Board Select Addressing - defines the board address in a board selection scheme that allows up to seven ZT 8832s to be mapped into the same STD bus memory and I/O address space. W43 † In In In In Out Out Out Out W42 W41 Board Address (hex) In In Out Out In In Out Out In Out In Out In Out In Out Board select disabled 1 2 3 4 5 6 7 †Factory default jumper configuration.
Jumper Configurations Table A-2 ZT 8832 Jumper Descriptions (continued). JUMPER # DESCRIPTION W44-W46 STD Bus Interrupt Selection - defines which STD bus interrupt request signal is driven by the ZT 8832. W44 In Out † Out W45 W46 Interrupt Signal Out In Out Out Out In INTRQ2* (STD bus pin 50) INTRQ1* (STD bus pin 37) INTRQ* (STD bus pin 44) †Factory default jumper configuration.
P1 A-14 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43 W44 W45 W46 Figure A–1. ZT 8832 Factory Default Configuration.
P1 W28 W29 W30 W31 W32 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43 W44 W45 W46 ZT 8832 ICP J4 W23 W24, W25 W26 W27 W20 W21 W22 W16, W17 W15 W9 W10 W11 W12 W13 W14 W7 W1 W2 W3 W4 W5 W6 W8 1 2 J5 3 J1 J2 J3 Jumper Configurations Figure A–2. Jumper Locations.
Jumper Configurations CUTTABLE TRACES The ZT 8832 supports several less popular options with cuttable traces. Cuttable traces are similar in function to jumper selections. The difference is that an option change made with a cuttable trace may require a trace cut and/or a short wire to be soldered between two pads. Cuttable traces are labeled CTx on the board, where x defines the cuttable trace number. Figures A-3 and A-4 on pages A-21 and A-22 illustrate cuttable trace locations.
Jumper Configurations Table A-4 ZT 8832 Cuttable Traces. TRACE # DESCRIPTION CT1, CT2 SBX Expansion Module Clock - selects the clock for the SBX expansion module. The default is a 10 MHz 50% duty cycle signal defined by the Intel SBX expansion module standard. The optional V40 clock is useful for custom SBX expansion module designs that must be synchronized to the local CPU.
Jumper Configurations Table A-4 ZT 8832 Cuttable Traces (continued). TRACE # DESCRIPTION CT6 Reserved for Ziatech use. CT7, CT8 Watchdog Timer Time Out - selects the delay from the watchdog timer strobe to the local reset. The watchdog timer includes two stages. The Stage 1 delay is measured from the watchdog strobe to the nonmaskable interrupt. The Stage 2 delay is measured from the watchdog strobe to the local CPU reset.
Jumper Configurations Table A-4 ZT 8832 Cuttable Traces (continued). TRACE # DESCRIPTION CT9, SBX Expansion Module Address Expansion - increases the number of I/O port addresses available to the SBX expansion module by increasing the number of address lines connected to the expansion module socket. The default connects address lines A0 through A6, providing 128 I/O port addresses for each of the two expansion module chip selects.
Jumper Configurations Table A-4 ZT 8832 Cuttable Traces (continued). TRACE # DESCRIPTION CT10 STD Bus AUX Ground - connects the STD bus AUX GND signal (P1 pins 53 and 54) to the STD bus logic GND signal (P1 pins 3 and 4). CT10 † In Out CT14 AUX GND connected to logic ground AUX GND not connected to logic ground STD Bus Dual Port RAM Addressing selects between the upper or lower 8 Mbytes for CPUs that have a 16 Mbyte addressing range. See page A-10. CT14 † In Out †Factory default configuration.
CT2 CT1 CT5 CT3 ZT 8832 ICP Jumper Configurations CT4 Figure A–3. Cuttable Trace Locations, Component Side.
Jumper Configurations CT6 CT8 CT7 CT9 CT11 CT12 CT13 CT14 CT10 Figure A–4. Cuttable Trace Locations, Solder Side.
Appendix B SPECIFICATIONS Contents Page ELECTRICAL AND ENVIRONMENTAL . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Battery Backup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 STD Bus Loading Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifications ELECTRICAL AND ENVIRONMENTAL Absolute Maximum Ratings Supply Voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 7 V Supply Voltage, AUX +V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13 V Supply Voltage, AUX -V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to -13 V Storage Temperature ZT 8832 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40˚ to +85˚ C ZT 88CT32 . . . . . . . .
Specifications STD Bus Loading Characteristics The unit load is a convenient method for specifying the input and output drive capability of STD bus cards. In the STD bus systems, one unit load is equal to one LSTTL load as follows: • Maximum high level input current: 20 µA • Maximum low level input current: -400 µA The STD bus unit load reflects input current requirements at worst case conditions over the recommended supply voltage and ambient temperature ranges.
Specifications Table B-1 ZT 8832 STD Bus Loading, P Connector.
Specifications Table B-2 ZT 8832 STD Bus Loading, E Connector.
Specifications MECHANICAL Card Dimensions & Weight The ZT 8832 meets the STD 32 bus specification for all mechanical parameters except for the component lead length protruding from the back of the board. The specification requires a maximum lead length of 0.093 inches, but the battery socket pins extend a maximum of 0.150 inches. Be sure the battery socket pins do not touch the adjacent board when installing the ZT 8832 into the STD bus card cage. In a card cage with 0.
Specifications 6.500 + - 0.025 o 0.015 X 45 CHAMFER 2 PL 0.100 FROM EDGE, NO COMPONENT PLACEMENT 2 PL 0.400 0.250 0.250 COMPONENT SIDE 3.610 4.500 0.015 X 45 o BEVEL BOTH EDGES +0.005 -0.015 0.06 RADIUS MAX 2 PL 0.15 X 45 o CHAM 3 PL 0.445 0.062 TOLERANCES 0.XXX = Connectors +-0.005 INCHES +-0.007 Figure B–1. Board Dimensions. The ZT 8832 has two card-edge connectors (P and E) and five headers to interface to the STD bus and application-specific devices (see Figure B-3).
Specifications STD 32 STD 32 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 E41 E42 E43 E44 E45 E46 E47 E48 E49 E50 E51 E52 E53 E54 E55 E56 E57 E58 E59 E60 E61 E62 E63 E64 E65 E66 E67 E68 P01 P02 P03 P04 P05 P07 P06 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P4
J1 J2 2 ZT 8832 ICP P1 J4 1 J5 3 J3 Specifications Figure B–3. Connector Locations.
Specifications J1: J1 is a nonlatching 26-pin (dual 13-pin) male transition connector with 0.1 inch lead spacing. J1 provides 24 digital I/O lines, fused +5 V ±10%, and ground. Table B-3 on page B-11 lists the pin assignments. These pin assignments enable the ZT 90068 cable to connect J1 directly to an I/O module mounting rack with 8, 16, or 24 positions. For applications not using this cable, the mating connector is a T&B Ansley #622-2630 or equivalent.
Specifications Table B-3 J1 Parallel Port Pinout.
Specifications Table B-4 J2 Serial Port (RS-232-C) Pinout. DTE Pin DCE 3 5 7 9 10 11 12 13 14 1,2,4 6,8 5 3 9 7 10 14 12 13 11 1,2,4 6,8 Signal Description TxD RxD RTS CTS DCD DSR RI GND DTR ----- Transmit Data Receive Data Request To Send Clear To Send Data Carrier Detect Data Set Ready Ring Indicator Ground Data Terminal Ready High Impedance No Connection Note: The Data Communication Equipment (DCE) and Data Terminal Equipment (DTE) options are jumper selectable for RS-232-C.
Specifications Table B-5 J2 Serial Port (RS-422/485) Pinout. Pin Signal Description 1 2 3 4 11 12 13 14 7,8 5,6,9,10 SDA SDB RSA RSB CSB CSA RDB RDA GND --- Send Data (negative) Send Data (positive) Request To Send (negative) Request To Send (positive) Clear To Send (positive) Clear To Send (negative) Receive Data (positive) Receive Data (negative) Ground No Connection Note: The J2 pin assignments permit ZT 8832s to be connected together using a straight cable and rotating one of the connectors 180˚.
Specifications Table B-6 J3 Counter/Timer and Interrupt Pinout.
Specifications Table B-7 J4 SBX Expansion Module Pinout.
Specifications Notes: [1] Signals ending with an asterisk are active low and signals without an asterisk are active high. [2] The V40 clock is optionally connected to MCLK with CT1 and CT2 (refer to the cuttable trace description on page A-17). This option is useful for designing SBX expansion modules synchronous to the ZT 8832 CPU. [3] These signals are not supported. The MPST* is a no-connect and TDMA is grounded.
Specifications Cables 40"+1" TB ANSLEY 622-1430 FEMALE .025" SQ. 14 PIN CONNECTOR POLARIZED TB ANSLEY 622-25S FEMALE 25 PIN "D" CONNECTOR TB ANSLEY 171-25 25 CONDUCTOR 28 GA. STRANDED FLAT CABLE TRIM 15-25 AT CONNECTOR BLUE WIRE PIN 1 PIN 1 P1 J1 P1 J1 17 5 18 6 19 7 20 1 1 8 2 3 4 5 6 7 14 2 15 3 16 4 9 10 11 12 13 14 Figure B–4. ZT 90014 Rev _ Serial I/O Cable.
Specifications 305 + 2cm (10' + 0.75") TB ANSLEY 622-5015 CARD EDGE CONNECTOR PIN 1 PIN 1 BLUE WIRE TB ANSLEY 622-0005 POLARIZING KEY SEE TABLE FOR PLACEMENT TB ANSLEY 622-5030 50 PIN FEMALE SOCKET TRANSITION CONNECTOR WITH POLARIZATION TAB. TB ANSLEY 171-50 50 CONDUCTOR 28 GA. STRANDED FLAT CABLE NO. OF MODULES 8 16 24 KEY LOCATION, BETWEEN PINS 29 AND 31 OR 17 AND 19 11 AND 13 23 AND 25 Figure B–5. ZT 90021 Rev _ Parallel I/O Cable.
Specifications 40"+1" TB ANSLEY 622-1430 FEMALE .025" SQ. 14 PIN CONNECTOR POLARIZED TB ANSLEY 622-25P MALE 25 PIN "D" CONNECTOR TB ANSLEY 171-25 25 CONDUCTOR 28 GA. STRANDED FLAT CABLE TRIM 15-25 AT CONNECTOR P1 J1 PIN 1 BLUE WIRE PIN 1 P1 J1 P1 J1 17 5 18 6 19 7 20 1 1 8 2 3 4 5 6 7 14 2 15 3 16 4 9 10 11 12 13 14 Figure B–7. ZT 90027 Rev _ Serial I/O Cable.
Specifications 7" Ref. 32"+ 1.0" 39"+ 1.0" 36"+ 1.0" AUGAT SIG CONNECTOR (NOTE 2) INSULATOR: SG113-3G2 DIVIDER: SG20-5P1 RETAINING CLIP: SG70-1P2 NOTE 1 T&B ANSLEY CONNECTOR: 622-5006E RETAINING CLIP: 622-0006 622-5030 PIN 50 PIN 50 PIN 49 AUGAT SG20-104P1 (3M 3415-0001) PIN 49 PIN 49 PIN 50 GROUND CONNECTION PIN 26 25 2 1 KEY (BOTTOM) AUGAT CABLE KEEPER SG71-2P1 AUGAT 28 GA.
Specifications Figure B–10. Standard Assembly Diagram.
Specifications TIMING The ZT 8832 meets the timing requirements outlined in the STD 32 bus specification. The SBX expansion module timings are given on the following pages. These pages assume the WCY1 and WCY2 V40 configuration registers are programmed to insert two wait states for all I/O and DMA transfers.
Specifications MA0-MA2 t11 MCS* t19 t17 t8 MWAIT* t25 t7 IOWRT* t10 t12 t13 t14 MD0-MDF Symbol t7 t8 t10 t11 t12 t13 t14 t17 t19 t25 Parameter Min Chip select setup to write low Chip select hold from write high Address setup to write low Address hold from write high Write pulse width Data setup to write high Data hold from write high Wait request pulse width Wait request delay from chip select Write delay from wait request 25 30 50 30 300 250 30 0 0 Max 4 ms 75 0 All times given in nanose
Specifications MDRQT t22 MDACK* t20 t21 IORD* OR IOWRT* Symbol t20 t21 t22 Parameter Min DMA acknowledge setup to read or write low DMA acknowledge hold from read or write high DMA request hold from read or write low 25 30 Max 150 All times given in nanoseconds Figure B–13. SBX Expansion Module DMA Timing.
Specifications 4.75V +5 VOLTS t9 or t18 RESET Symbol t9 t18 Parameter Min Power up reset pulse width Reset pulse width 50 50 µs Max All times given in nanoseconds except where otherwise indicated Figure B–15. SBX Expansion Module Reset Timing.
Appendix C CUSTOMER SUPPORT Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZT 8832 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision 0.1 . . . . . . . . .
Customer Support REVISION HISTORY ZT 8832 Revision 0 The ZT 8832 was originally released on 7/3/89 as Revision 0. Revision 0.1 There were no functional changes at this revision. Revision 0.2 A change was made to the ZT 8832 for Revision 0.2 that affects when the STD bus control port and local control port are reset. The Revision 0.1 board reset these control ports in response to an STD bus SYSRESET* only.
Customer Support Support was added for 24-bit addressing in either the upper or the lower 8 Mbyte region. See page A-10 for more information. Revision 0.5 No functional changes. ZT 88CT32 Revision 0 The ZT 88CT32 was originally released as Revision 0. Revision 0.1 Pullup resistor packs RP7 and RP8 were changed from 100 kΩ to 10 kΩ. This eliminates problems experienced with SBX expansion modules that drive signals such as wait request with an undetermined open collector device. Revision 0.
Customer Support TECHNICAL ASSISTANCE You can reach Ziatech’s Customer Support Service at the following number: Corporate Headquarters: (805) 541-0488 (805) 541-5088 (FAX) You can also use your modem to leave a message on the 24-hour Ziatech Bulletin Board Service (BBS) by calling (805) 541-8218. The BBS will also provide you with current Ziatech product revision and upgrade information.
Customer Support RELIABILITY Ziatech has taken extra care in the design of the ZT 8832 to ensure reliability. The four major ways in which reliability is achieved are: 1. The product was designed in top-down fashion, using the latest in hardware and software design techniques, so that unwanted side effects and unclean interactions between parts of the system are eliminated. 2.
Customer Support RETURNING FOR SERVICE Before returning any of Ziatech’s products, you must obtain a Returned Material Authorization (RMA) number by calling (805) 541-0488. We will need the following information to expedite the shipment of a replacement to you: 1. Your company name and address for invoice 2. Shipping address and phone number 3. Product ID number 4.
Customer Support ZIATECH 5+5 WARRANTY FIVE-YEAR LIMITED WARRANTY Products manufactured by Ziatech Corporation are covered from the date of purchase by a five-year warranty against defects in materials, workmanship, and published specifications applicable to the date of manufacture. During the warranty period, Ziatech will repair or replace, solely at its option, defective units provided they are returned at customer expense to an authorized Ziatech repair facility.
Customer Support SPECIAL EXTENDED WARRANTY OPTION In addition to the standard five-year warranty, Ziatech offers, for a nominal fee, an extended period of warranty up to five extra years. This extended warranty period provides similar coverage and conditions as stated above in the five-year limited warranty agreement.
Appendix D GLOSSARY backplane The edge of the board that inserts into the STD bus connector. This term is generally used to define the location of signals that are routed across the STD bus. BAU Bus Arbitration Unit. Section of the CPU that controls which internal or external bus master has access to the buses at any given time. BCD Binary Coded Decimal. Representation of the cardinal numbers 0 through 9 by ten binary codes. Each binary code is 4 binary digits long. BIU Bus Interface Unit.
Glossary CNTRL* Control. This STD bus signal (pin 50) was used in previous designs for special clock timing on peripheral boards. It may also be used as an interrupt request, INTRQ2*, on the backplane. DCE Data Communication Equipment. One of two possible orientations (DCE or DTE) for drivers and receivers in the RS-232-C serial communications protocol. DCU DMA Control Unit. Section of the CPU that controls high speed data transfer between I/O and memory devices. DMA Direct Memory Access.
Glossary frontplane The edge of the board on which the extractor is located, opposite to the backplane. This term is generally used to define the location of user interface signals. ICU Interrupt Control Unit, on the V40 CPU. INTRQ* INTRQ1* INTRQ2* Interrupt Requests. These STD-80 signals are processor card input signals that conditionally interrupt the program when enabled by a specific program instruction. INTRQ2* was formerly called CNTRL*; see CNTRL*.
Glossary prefetch Instructions are fetched and stored into a queue on the microprocessor prior to execution in order to optimize performance. push A stack operation that stores one byte onto the top of the processor stack. RS-232-C An acronym for Required Standard 232 of the Electronics Industry Association. Interface standard between Data Terminal Equipment and Data Communication Equipment, employing serial binary data exchange.
Glossary WCU Wait Control Unit. Section of the CPU that can define a different number of wait states for each of the three areas of the memory space.
INDEX -AACC - Asynchronous Communication Controller . . . . . . . . . . . 1-8, 11-1 asynchronous data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 DCE/DTE jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index -Bbackplane, definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 battery backup for local RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 BAU - Bus Arbitration Unit (V40) . . . . . . . . . . . . . . . .
Index definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 CNTRL* (INTRQ2*), definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 commonly asked questions, ZT 8832 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 connectors connector locations drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 J4 (custom I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index CT10 (STD bus AUX GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20 CT14 (STD bus dual port RAM addressing) . . . . . . . . . . . . . . . . . . . . A-20 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 custom I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 frontplane connector J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index DMA controller (V40) (see DCU - DMA Control Unit) . . . . . . . . . . 9-1 DMD - DMA Mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 DMK - DMA Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 DOS MPX development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4, 3-3 installing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index -Ggetting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 -IICU - Interrupt Control Unit (V40) . . . . . . . . . . . . . . 1-9, 3-17, 5-22, 8-1 automatic priority rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Interrupt Enable register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Interrupt Generation Logic (V40 SCU) . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Interrupt Identify register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Interrupt Initialization Words 1-4 (IIW1-IIW4) . . . . . . . . . . . . . . 8-6, 8-8 Interrupt In-Service register (V40 ICU) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Interrupt Mask register (V40 ICU) . . . . . . .
Index -LLight Emitting Diode (LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Line Control register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Line Status register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 local control port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Modem Control block (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Modem Control register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Modem Status register (82050 ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 Mode register (V40 TCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 modes 0-5 (count modes, V40 TCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index frontplane connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2, B-10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 I/O module mounting racks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 mixing I/O in a single port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index V40 SCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 devices affected by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 return for service . . . . . .
Index I/O port addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 programmable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index system requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 -TTCKS - Timer Clock Selection register . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 TCU - Counter/Timer Control Unit (V40) . . . . . . . . . . . . . 1-9, 5-21, 7-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index BIU - Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 CGU - Clock Generator Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 commonly asked questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index W41-W43 (board select addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 W44-W46 (STD bus interrupt selection) . . . . . . . . . . . . . . . . . . . . . . . A-13 wait-state generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
