Specifications

Interrupt Controller (8259A)
PROGRAMMABLE REGISTERS
The PIC is initialized with the Initialization Control Words 1 through
4 (ICW1-4). This must take place before enabling CPU interrupts,
since the 8259A does not receive a power-up reset pulse and is in an
undetermined state until initialized. Operation of the PIC is then
controlled with Operation Control Words 1 through 3 (OCW1-3),
which handle operation and read or write access to various registers
within the PIC.
All registers within the PIC are addressed at I/O addresses 0020h and
0021h. As may be expected, a specific sequence of read and write
operations is needed to pass multiple bytes through two I/O addresses.
The following subsections describe these registers and the methods
used to access them. Table 12-1 summarizes the register addresses
and where each is described within this chapter. Refer to the figures
on pages 12-13 and 12-17 for the format of each Control Word.
Table 12-1
PIC Registers.
Pages
Address Register Operation
Described
0020h IRR, ISR, IL
†
Read 12-8, 12-9
0020h ICW1, OCW2, OCW3 Write 12-12, 12-18
0021h IMR Read 12-8
0021h ICW2 - ICW4, OCW1 Write 12-14,
12-18
†When the PIC is programmed for poll mode (bit 2 = "1" in OCW3), this address can
be used to read the binary status of the highest priority Interrupt Level (IL) requesting
service.
12-11