Specifications

Introduction
Wait-State Generator
To accommodate I/O and memory boards needing more time for
access, the ZT 8809A contains a one wait-state generator. If enabled,
it inserts one wait-state (clock cycle) within the normal four-clock bus
cycle to increase it to five clocks. This gives memory and I/O boards
additional time between address valid time and the end of the bus
cycle to complete an access.
Direct Memory Access
(DMA)
External DMA controllers are supported by the ZT 8809A via the
BUSRQ* (pin 42) and BUSAK* (pin 41) STD bus control signals. A
request for the bus is made to the ZT 8809A via BUSRQ* pin 42, and
the ZT 8809A responds with BUSAK* once the microprocessor has
signaled its release of the bus. When the DMA transfer is complete,
the DMA device releases BUSRQ* and the ZT 8809A then responds
by releasing BUSAK*. DMA is supported on the ZT 8809A for all
on-board EPROM and RAM, with the exception of the 32 Kbyte
static RAM.
Optional Battery
Backup
All RAM and the real-time clock may be selectively battery-backed
with a 3.9 V, 1 Amp-hour lithium battery, which is shipped as a
standard option with the ZT 8809A STD DOS systems. When DC
power falls below 4.75 V, the battery power is switched in and
remains until power is again at that level. At the same time, the
DCPWRDWN* STD bus signal (pin 6) is driven active (low) to warn
other boards in the system of low DC voltage.
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