Specifications

Serial Communications (16C452)
Table 8-3
16C452 Addressable Registers Summary (continued).
Register Address
Bit
No.
0 DLAB = 1 1 DLAB = 1467
Divisor
Latch (LSB)
Divisor
Latch (MSB)
Modem
Control
Register
Modem
Status
Register
Scratchpad
Register
DLL DLMMCR MSR SCR
0D0D8
Data
Terminal
Ready
(DTR)
Delta Clear
to Send
(DCTS)
SCR0
1
D1 D9
Request to
Send
(RTS)
Delta Data
Set Ready
(DDSR)
SCR1
2 D2 D10
OUT1
(Not
available
externally)
Trailing Edge
Ring
Indicator
(TERI)
SCR2
3 D3 D11
OUT2
(Interrupt
output
enable)
Delta Data
Carrier
Detect
(DDCD)
SCR3
4 D4 D12Loop
Clear to
Send (CTS)
SCR4
5 D5 D130
Data Set
Ready (DSR)
SCR5
6 D6 D140
Ring
Indicator
(RI)
SCR6
70
5
Line Status
Register
LSR
Data Ready
(DR)
Overrun
Error (OE)
Parity
Error (PE)
Framing
Error (FE)
Break
Interrupt
(BI)
Transmit
Holding
Register
(THRE)
Transmit
Empty
(TEMT)
0
Data Carrier
Detect
(DCD)
D7 D15SCR7
8-19