Specifications

Numeric Data Processor (8087)
COPROCESSOR INTERFACE
Communication between the 8087 and the V20 occurs over the
request/grant, queue-status, and busy lines. The 8087 uses the
request/grant line to obtain control of the local bus for data transfers.
The request/grant sequence is as follows:
1. A pulse, one clock wide, is passed to the CPU to indicate a local
bus request by the 8087.
2. The 8087 waits for the grant pulse. When received, the 8087
initiates a bus transfer in the following clock cycle.
3. The 8087 generates a release pulse to the CPU one clock cycle
after the completion of the last 8087 bus cycle.
The V20 queue-status lines QS0 and QS1 synchronize the fetching
and decoding of instructions by two devices. Table 7-1 below shows
the cycles indicated by the encoding of QS1 and QS0.
Table 7-1
Queue-Status Line Functions.
FUNCTION QS1 QS0
No Operation 0 0
First OP Code Byte from Queue 0 1
Empty the Queue 1 0
Subsequent Byte from Queue 1
1
7-7