Specifications

CPU Description
RESET STATE
The ZT 8809A contains on-board power-fail detection logic that
detects DC, and optionally AC, power failure. This topic is covered
more fully in Chapter 13. The DC power failure mechanism is used to
detect a valid Vcc level and assert reset to the STD system for
approximately 600 milliseconds after that time. Reset to the system is
sent on the STD bus via the SYSRESET* signal, pin 47.
After power-up, reset may be asserted to the ZT 8809A via push-
button reset (PBRESET*), which is pin 48 on the STD bus.
Debouncing circuitry on board allows for any pushbutton switch or
logic level to drive PBRESET* low. The driver of PBRESET* must
meet the following requirements:
• open collector if a logic gate
• remain active low for a minimum of 1.0 milliseconds
After a power-up or pushbutton reset, the microprocessor will first
access memory location FFFF0h. This is the location of the on-board
EPROM at socket 5D1. The processor then executes the instruction at
that address, and the remainder of the program may reside anywhere
in existing EPROM or RAM memory.
The reset state of all of the on-board devices is detailed under each
device’s description in the following chapters.
6-20