CPU Description
Figure 6-3 illustrates the signals required for a transfer between an
STD bus DMA controller and the ZT 8809A.
A0-A19
D0-D7
BUSRQ*
BUSAK*
RD*
WR*
MEMRQ*
MCSYNC*
STD BUS I/O OR
MEMORY WITH DMA
ZT 8808A/
ZT 8809A
Figure 6–3. DMA With STD Bus Controller.
6-19
