Specifications

Chapter 6
CPU DESCRIPTION (V20)
Contents Page
V20 OVERVIEW ................................................ 6-2
Segment Registers
............................................ 6-3
Program Counter (PC) [IP]
.................................... 6-5
Prefetch Pointer (PFP)
........................................ 6-6
General Purpose Registers
..................................... 6-6
Pointers and Index Registers
................................... 6-7
Program Status Word (PSW) [FL]
.............................. 6-8
V20 ARCHITECTURAL ENHANCEMENTS
....................... 6-9
Dual Data Bus
............................................... 6-9
Effective Address Generator
................................... 6-9
16/32-Bit Temporary Shift Registers (TA,TB)
.................. 6-10
Loop Counter (LC)
.......................................... 6-10
Program Counter (PC) and Prefetch Pointer (PFP)
.............. 6-10
Enhanced and Unique Instructions
............................. 6-11
MODE OPERATIONS - 8080 EMULATION MODE
............... 6-12
Break for Emulation (BRKEM)
............................... 6-14
Return From Emulation (RETEM)
............................ 6-14
Call Native Routine (CALLN)
................................ 6-15
Return from Interrupt (RETI)
................................. 6-15
Register Use in Emulation Mode
.............................. 6-16
DMA SUPPORT
................................................ 6-18
RESET STATE
................................................. 6-20
WAIT-STATE GENERATOR
..................................... 6-21
6-1