Specifications

Application Examples
; REG #1 INTERRUPT ENABLE REG (W)
PORT_INTEN EQU 001H ; INTERRUPT EN.
PORT_DLAMB EQU 001H ; IF DLAB=1, MSB DIV.
ERBI EQU 01H ; EN INTR ON RECV
EIRBI EQU 01H ; EN INTR ON RECV
EIRBO EQU 02H ; EN INTR ON XMT
ELSI EQU 04H ; EN LINE STATUS
EDSSI EQU 08H ; EN MODEM STATUS
;
; REG # 2 INTERRUPT STATUS REG (R)
PORT_INSTAT EQU 002H ; INTERRUPT STATUS
INTPND EQU 0FEH ; INTERRUPT PENDING
RVLNS EQU 06H ; RECV LINE INTR
RECDA EQU 04H ; RECV DATA AVAIL
TXHRE EQU 02H ; XMTR. HOLD EMPTY
MODST EQU 00H ; MODEM STATUS INTR
;
; REG # 3 LINE CONTROL REG (R/W)
PORT_LINEC EQU 003H ; LINE CONTROL REG
WL5 EQU 00H ; 5 BIT WORD
WL6 EQU 01H ; 6 BIT WORD
WL7 EQU 02H ; 7 BIT WORD
WL8 EQU 03H ; 8 BIT WORD
STB EQU 04H ; 2 STOP BITS
PEN EQU 10H ; PARITY ENABLE
EPS EQU 20H ; STICK PARITY
SBK EQU 40H ; SET BREAK
DLAB EQU 80H ; DIV LATCH ACCESS
; DIVISOR LATCH VALUES (REG#3, DLAB=1)
BD111 EQU 1047 ; 110 BAUD COUNT
BD301 EQU 384 ; 300 BAUD COUNT
BD122 EQU 96 ; 1200 BAUD COUNT
BD242 EQU 48 ; 2400 BAUD COUNT
BD362 EQU 32 ; 3600 BAUD COUNT
BD482 EQU 24 ; 4800 BAUD COUNT
BD962 EQU 12 ; 9600 BAUD COUNT
BD193 EQU 6 ; 19.2K BAUD COUNT
;
; REG #4 MODEM CONTROL REG (W)
PORT_MODC EQU 004H ; MODEM CONTROL
DTR EQU 01H ; DATA TRML READY
RTS EQU 02H ; REQ TO SEND
OUT2 EQU 08H ; ENABLE INTERRUPT
DIAG EQU 10H ; DIAGNOSTIC MODE
;
; REG #5 LINE STATUS REG (R)
PORT_LINST EQU 005H ; LINE STATUS
DR EQU 01H ; DATA READY
ORE EQU 02H ; OVERRUN ERROR
PE EQU 04H ; PARITY ERROR
FE EQU 80H ; FRAMING ERROR
BKI EQU 10H ; BREAK INTR
THRE EQU 20H ; XMTR HOLD EMPTY
TSRE EQU 40H ; XMTR SHIFT EMPTY
;
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