ZT 8808A/8809A V20 Single Board Computers OPERATING MANUAL FOR ZT 8808A/8809A REVISION A ZT 88CT08A/88CT09A REVISION A May 1, 1993 1050 Southwood Drive San Luis Obispo, CA 93401 USA FAX (805) 541-5088 Telephone (805) 541-0488
ZIATECH WARRANTY Ziatech Hardware: Within two years of shipping date, Ziatech will repair or replace products which prove to be defective in materials and/or workmanship, provided they are promptly returned to Ziatech at customer’s expense and have not been repaired, altered, or damaged by non-Ziatech personnel. Service after warranty is available at a predesignated service charge. Batteries are not covered by this warranty. No other warranty is expressed or implied.
CUSTOMER SUPPORT If you have a technical question, please call Ziatech’s Customer Support Service at one of the following numbers. Corporate Headquarters: (805) 541-0488 (805) 541-5088 (FAX) You can also use a modem to leave a message on the 24-hour Ziatech Bulletin Board Service (BBS) by calling (805) 541-8218. The BBS will provide you with current Ziatech product revision and upgrade information.
PREFACE The ZT 8808A and ZT 8809A are single board computers designed primarily for DOS applications on the STD bus. The combination of the 8088-compatible V20 microprocessor with RAM, EPROM, serial ports, a printer port, timers, and a real-time clock makes a hardwarecompatible PC viable for compact industrial applications. This manual describes the operation and use of the ZT 8808A/8809A.
Preface STD bus compatibility, serial communications, interrupts, direct memory access, power-fail protection, and battery backup. Chapter 4, "Application Examples," provides specific examples of the ZT 8809A in operation, including code to implement these applications. The examples demonstrate the use of interrupts, timers, and the real-time clock. Chapter 5, "Memory and I/O Capability," focuses on the memory and input/output organization of the V20 microprocessor relative to the ZT 8809A.
Preface Chapter 11, "Counter/Timers (8254)," describes the main components of the three programmable 16-bit counter/timers implemented in an Intel 8254 chip on the ZT 8809A. This chapter describes the method used to program the counter/timers and their use by STD DOS and STD ROM. Chapter 12, "Interrupt Controller (8259A)," describes the features and operation of the Intel 8259A Programmable Interrupt Controller (PIC).
CONTENTS I. INTRODUCTION Chapter 1. INTRODUCTION 1-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ZT 88CT08A and ZT 88CT09A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 FEATURES OF THE ZT 8809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 V20 (uPD70108) Processor . . . . . . . .
Contents Physical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 INSTALLING THE ZT 8809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Configuring the ZT 8809A for STD ROM . . . . . . . . . . . . . . . . . . . . . . .
Contents Chapter 4. APPLICATION EXAMPLES 4-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 EXAMPLE 1-A: USING SIMPLE INTERRUPTS . . . . . . . . . . . . . . . . . . . 4-3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Software Outline . . . . . . . . . . . . . .
Contents Prefetch Pointer (PFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Pointers and Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Program Status Word (PSW) [FL] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 V20 ARCHITECTURAL ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . .
Contents Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Chapter 12. INTERRUPT CONTROLLER (8259A) 12-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 I/O PORT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 OPERATION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Interrupt Request Register (IRR) .
Contents IV. APPENDICES Appendix A. JUMPER CONFIGURATIONS A-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 JUMPER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Appendix B. SPECIFICATIONS B-1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 ELECTRICAL AND ENVIRONMENTAL . . . . . . . . . . . . . . . . . . . . . . . . .
TABLES Table 3–1 Table 3–2 Table 5–1 Table 5–2 Table 5–3 Table 6–1 Table 6–2 Table 6–3 Table 7–1 Table 8–1 Table 8–2 Table 8–3 Table 8–4 Table 8–5 Table 9–1 Table 9–2 Table 9–3 Table 9–4 Table 9–5 Table 11–1 Table 11–2 Table 11–3 Table 12–1 Table A–1 Table A–2 Table B–1 Table B–2 Table B–3 Table B–4 Table B–5 Table B–6 Table B–7 Table B–8 Processor Speed Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Serial Communications Standards. . . . . . . . . . . . . . . . . . . . .
Tables Table B–9 Table B–10 Table B–11 J5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17 J6 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18 J7 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ILLUSTRATIONS Figure 1–1 Figure 2–1 Figure 2–2 Figure 2–3 Figure 2–4 Figure 2–5 Figure 3–1 Figure 3–2 Figure 3–3 Figure 3–4 Figure 3–5 Figure 3–6 Figure 5–1 Figure 5–2 Figure 5–3 Figure 5–4 Figure 5–5 Figure 5–6 Figure 5–7 Figure 5–8 Figure 6–1 Figure 6–2 Figure 6–3 Figure 7–1 Figure 8–1 Figure 8–2 Figure 8–3 Figure 9–1 Figure 10–1 Figure 10–2 Figure 10–3 Figure 11–1 Figure 11–2 ZT 8809A Functional Block Diagram. . . . . . . . . . . . . . . . . . 1-5 Non-DOS Factory Default Jumper Configuration. . . . . .
Illustrations Figure 11–3 Figure 11–4 Figure 11–5 Figure 11–6 Figure 12–1 Figure 12–2 Figure 12–3 Figure 12–4 Figure 12–5 Figure A–1 Figure A–2 Figure A–3 Figure A–4 Figure A–5 Figure A–6 Figure A–7 Figure A–8 Figure A–9 Figure A–10 Figure A–11 Figure A–12 Figure A–13 Figure A–14 Figure A–15 Figure A–16 Figure B–1 Figure B–2 Figure B–3 Figure B–4 Figure B–5 Figure B–6 Figure B–7 Figure B–8 Figure B–9 Figure B–10 Figure B–11 Figure B–12 Figure B–13 Figure B–14 Control Word Format. . . . . . . . . . . . . .
Chapter 1 INTRODUCTION Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ZT 88CT08A and ZT 88CT09A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 FEATURES OF THE ZT 8809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 V20 (uPD70108) Processor . . . . . . . . . . . . . . .
Introduction A performance increase over 8088-based STD CPU boards is achieved in part by the use of the NEC V20 microprocessor. This is an 8088 compatible processor with a superset of the 8088 instruction set. The V20 is a CMOS device with a standby mode, which results in lower power consumption. The ZT 8808A/8809A and 88CT08A/88CT09A boards also provide an increase in memory capacity over the earlier non-"A" versions (ZT 8808/8809 and 88CT08/88CT09).
Introduction All RAM and the real-time clock may be optionally battery-backed by a 1 Amp-hour lithium battery. DC power failure detection is provided to switch to the battery backup mode during +5 VDC failure. AC power failure detection is possible with the use of an optional AC/DC converter. Detection of AC power failure provides time for the processor to save critical data in battery-backed RAM before impending +5 VDC failure.
Introduction FEATURES OF THE ZT 8809A • • • • STD-80 and STD 32 bus compatible Optional CMOS versions available 8088/8086 code compatible Four 32-pin memory sockets, configurable for – – • • • • • • • • • • • • • • • • • • • 1-4 1 EPROM and 3 RAMs or 2 EPROMs and 2 RAMs Acceptable RAM sizes are 32 Kbytes to 512 Kbytes Acceptable EPROM sizes 16 Kbytes through 256 Kbytes One 32 Kbyte static RAM Real-time clock (DS 1215) Optional battery backup for all RAM and real-time clock AC/DC power-fail protection
Introduction ZT 8809A Optional Battery Backup 3 Counter/ Timers RS-232-C Serial Interrupt Controller RS-232-C/ RS-422/485 Serial 32K RAM (Optional Battery Backup) V20 CPU Clock Slowdown and Halt/ Restart AC/DC PowerFail Centronics Printer I/O Real-time Clock 256K RAM & 256K ROM or 384K RAM & 128K ROM (RAM Optionally Battery-backed) Figure 1–1. ZT 8809A Functional Block Diagram.
Introduction FUNCTIONAL BLOCKS Figure 1-1 illustrates the ZT 8809A’s functional blocks. A brief description of each block follows. V20 (uPD70108) Processor The NEC V20 is an 8088-compatible microprocessor with a 16-bit internal data bus and an 8-bit external data bus. The V20 executes all code written for the 8088/8086 family of microprocessors and includes a superset of their instruction set.
Introduction Wait-State Generator To accommodate I/O and memory boards needing more time for access, the ZT 8809A contains a one wait-state generator. If enabled, it inserts one wait-state (clock cycle) within the normal four-clock bus cycle to increase it to five clocks. This gives memory and I/O boards additional time between address valid time and the end of the bus cycle to complete an access.
Introduction Jumpers are provided to select whether the following three groups of devices, either individually or as a whole, are to be battery-backed: • Real-time clock and 32 Kbyte RAM • Two RAM sockets • ROM/RAM socket when RAM is present This conserves battery power exclusively for those devices that require backup. AC/DC Power-Fail Detection DC power-fail detection senses when DC voltage drops below 4.75 V. This signals the board to switch into battery backup mode, as described above.
Introduction Real-Time Clock The real-time clock on the ZT 8809A is a Dallas Semiconductor DS 1215. It keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years. The clock automatically corrects for leap years, and adjusts for months with fewer than 31 days. It may be battery-backed by the optional battery. The real-time clock shares its address space with the 32 Kbyte static RAM.
Introduction Counter/Timers The ZT 8809A has three independent 16-bit counter/timers, each of which can be used as a timer or event counter. The clock frequency driving each of these timers is a 1.19318 MHz oscillator. For timers 1 and 2, the clock input may be jumpered to receive the frontplane connector J4 signal, which may be an external frequency or event input. The six programmable counter/timer modes are as follows: 1. Interrupt on end of count 2. Frequency divider 3. Square wave generator 4.
Introduction Interrupts The programmable interrupt controller (PIC) on the ZT 8809A is an Intel 8259A-2 or equivalent. It has eight interrupt inputs that can be prioritized in software. Its output drives the CPU interrupt input. All PIC interrupt inputs may be jumper selected between various onboard sources and the five frontplane and three backplane sources. Factory default assigns the STD DOS compatible interrupt selections as described by jumper descriptions W2-11 in Appendix A.
Introduction Centronics Printer/General Purpose I/O Port A Centronics printer interface is included on the ZT 8809A. It may drive a Centronics-compatible printer directly. The printer interface can also be used for general purpose I/O. It consists of eight I/O lines for data, four open collector I/O lines for control, and five input lines for status. The open collector lines have internal 2.5 kΩ pullups to Vcc.
Introduction Clock Slowdown & Halt Restart (CMOS boards only) For power conservation, the ZT 88CT08A and ZT 88CT09A contain two features to slow down or stop processor execution programmatically. These are the clock slowdown and halt with interrupt restart features, provided by a special Harris Semiconductor 82C85 clock chip that replaces the 82C84A normally shipped on the ZT 8809A board. Clock slowdown divides the existing clock frequency by 256, allowing a selection between 5 MHz and 19.
Chapter 2 GETTING STARTED Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 UNPACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 WHAT’S IN THE BOX? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 SYSTEM REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Physical Requirements .
Getting Started OVERVIEW This chapter includes all the information you need to properly install the ZT 8809A into an STD bus card cage. You should read this chapter and Chapter 3, "Theory of Operation," before you attempt to use the board. Remember, unless specifically stated otherwise, all references to the ZT 8809A also pertain to the ZT 8808A, ZT 88CT08A, and ZT 88CT09A. UNPACKING Please check the shipping carton for damage.
Getting Started WHAT’S IN THE BOX? The items listed below are included in a standard ZT 8809A order. The list does not include options such as system level software or cabling. Refer to the packing list for a complete list of items shipped. When ordering specific system level software options with the ZT 8809A, refer to the software manual for a list of the items that should be included. • ZT 8808A or ZT 8809A Single Board NEC V20 Computer or ZT 88CT08A or ZT 88CT09A Single Board 80C88 Computer.
Getting Started SYSTEM REQUIREMENTS Physical Requirements The ZT 8809A is designed to be used in an STD bus system. It is therefore physically and electrically compatible with the STD-80 bus standard. It should normally be mounted in one slot of an STD bus card cage. If the zSBC 337 module containing the 8087 Numeric Data Processor is mounted on the board, it occupies two slots of the card cage unless the end slot is used.
Getting Started Important Note: The ZT 8809A CPU uses an 82C84A or 82C84B as the clock generator. The following special considerations should be observed regarding the +5 VDC power supply: • The +5 VDC power supply should never have a rise time faster than 1 V per millisecond. • Use switcher-type power supplies if possible because their turn-on times are generally slower than linear power supplies.
Getting Started Environmental Requirements The ambient temperature must be maintained at 0˚ to +65˚ Celsius for proper operation and to avoid possible damage to the ZT 8809A (the ZT 88CT08A and ZT 88CT09A allow for a lower power requirement and wider temperature range, detailed in Chapter 13). Relative humidity should be less than 95% at 40˚ C, non-condensing.
Getting Started INSTALLING THE ZT 8809A The fastest way to begin using the ZT 8809A is with the addition of development software available from Ziatech. The STD ROM development system allows you to download application software developed on an IBM PC (or equivalent) through a serial port onto the ZT 8809A. In addition to download and upload capabilities, STD ROM uses Borland’s Turbo Debugger, which provides a wide variety of commands for debugging software.
Getting Started TIMER COUNTER W12 W29 W30 W31 W32 LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 32K SRAM B A STD ROM W49 W68 A B W48 W47 B A A B W46 A B W37 ZT8809A REV. A W16 W17 W18 W19 W20 W21 W22 COM1 A W4 W5 W6 W7 W8 W9 W10 W11 W1 W14 W3 A W15 B W2 A B W13 COM2 W23 W24 W25 W26 W27 W28 INTERRUPTS W66 B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A A B W50 W60 W62 W63 W61 Figure 2–1. Non-DOS Factory Default Jumper Configuration.
Getting Started Configuring the ZT 8809A for STD ROM The STD ROM development system is available as an option to the ZT 8809A for software development. If STD ROM is ordered along with the ZT 8809A, the board is preconfigured and tested at the factory prior to shipment. If the system has been altered or the ZT 8809A rejumpered and the system does not function properly, refer to the following instructions and to Figure 2-1 for configuring your ZT 8809A.
Getting Started STD ROM Cable Requirements A serial link is required for the STD ROM system between frontplane connector J1 and the IBM PC or compatible. The cable shipped with the STD ROM system should be used for this purpose. Plug this cable into connector J1 of the ZT 8809A. The IBM AT requires an adapter cable for its serial port with a 25-pin male D-type connector on one side and a 9-pin female D-type connector on the other. The Ziatech part number for this adapter cable is ZT 90026.
Getting Started Note: This configures sockets 3D1 and 5D1 for 64 Kbyte ROMs and sockets 7D1 and 9D1 for 128 Kbyte RAMs. Memory mapping information may be found in the jumper configuration tables for W55W59 in Appendix A. Powering Up STD ROM Once the EPROM, RAM, jumpers, and cable are correctly configured, install the ZT 8809A into the STD bus card cage. Be sure to attach the D-type connector end of the cable to the appropriate IBM PC or compatible.
Getting Started • 2-12 Some things to check if the system is not working: 1. Two ZT 8809A frontplane connectors accept the ZT 90014 serial cable. STD ROM works only in serial port 1 at J1. 2. If a PC is used that has more than one 25-pin male connector, be sure the serial cable is plugged into COM1. 3. Check to see the EPROM and RAM chips are installed in the proper sockets. EPROM should be installed in socket 5D1. RAM should be installed in socket 7D1. 4.
Getting Started Configuring the ZT 8809A for STD DOS STD DOS is an optional MS-DOS operating system available for the ZT 8809A V20 processor board. If the ZT 8809A and STD DOS are ordered together, Ziatech configures the ZT 8809A properly prior to shipment and tests it as a system. If the ZT 8809A and STD DOS are ordered separately, or the ZT 8809A was altered in any way after shipment, instructions for installing and booting STD DOS on the ZT 8809A are in the STD DOS System Manual.
Getting Started TIMER COUNTER W12 W29 W30 W31 W32 LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 W66 W68 128K RAM 128K RAM B A 256K EPROM W49 128K EPROM W47 B A A B W48 W37 A B W46 A B B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A B W50 A W60 W62 W63 W61 Figure 2–2. ZT 8809A Configured For STD DOS. 2-14 ZT8809A REV.
Getting Started STD DOS Memory Requirements The STD DOS/BIOS software is shipped in one EPROM for installation onto the ZT 8809A at socket location 5D1 (see Figure 2-2). Install the EPROM only at a static-free workstation. Orient pin 1 properly, to the lower left with the board oriented component side up, goldfingers to the left. STD DOS requires at least 128 Kbytes of static RAM, although the STD DOS system is shipped with 256 Kbytes.
Getting Started STD DOS Cable Requirements If the STD DOS system is not a Stand Alone (SA) system, a serial link is required between the ZT 8809A and a terminal or PC. Refer to the STD DOS System Manual for cabling requirements. The ZT 90039 optional printer cable is available from Ziatech for use with a Centronics printer port. Install this cable into connector J6, with the keying notch oriented to the inside of the board.
Getting Started Powering Up STD DOS Be sure the ZT 8809A is seated securely into the card cage and the power switch is off. Plug the card cage into your power source. Refer to the following instructions appropriate to your configuration (PCAssisted with a host computer, PC-Assisted with a terminal or video board, or Automation Engine). PC-Assisted with a host computer - An IBM PC or compatible is used to communicate with the ZT 8809A STD DOS system. 1.
Getting Started PC-Assisted with a terminal or video board - The PC-Assisted system can also communicate with a terminal via COM2, or through a Ziatech video board with keyboard support. 1. If you are using a terminal for communication with the ZT 8809A STD DOS system, connect the system’s serial cable from the proper serial port to the terminal. 2. If you are using a video board: 3. a) The ZT 8844 EGA video board is shipped configured for a monochrome monitor.
Getting Started MEMORY ADDRESSING Figures 2-3 and 2-4 on pages 2-20 and 2-21 show the memory addresses occupied by the ZT 8809A, for both STD DOS and STD ROM. See also Appendix A for the tables describing the memory configuration jumpers W55-W59. Access to on-board memory and the backplane is through the full 8088 20-bit memory address, allowing for 1 Mbyte of memory in the system. On-board memory consists of one 32 Kbyte static RAM and four 32-pin byte-wide sockets.
Getting Started FFFFFh 256 Kbyte ROM Drive w/ 256 Kbyte EPROM DFFFFh D8000h 32 Kbyte RAM Drive and Timekeeper C0000h 5FFFFh 40000h 3FFFFh 128 Kbyte ROM Drive w/ 128 Kbyte EPROM On-Board RAM w/ 128 Kbyte RAMs 0h Note: Shaded portion represents off-board memory address space. Figure 2–3. STD DOS Factory Default Memory Map.
Getting Started FFFFFh 128 Kbytes w/ 64 Kbyte EPROM E0000h DFFFFh D8000h D7FFFh 32 Kbyte RAM Drive and Timekeeper 40000h 3FFFFh On-board RAM w/ 128 Kbyte RAMs 0h Note: Shaded portion represents off-board memory address space. Figure 2–4. STD ROM Factory Default Memory Map.
Getting Started I/O ADDRESSING Figure 2-5 on page 2-23 shows the I/O addresses occupied by the ZT 8809A, for both STD DOS and STD ROM systems. I/O accesses are made via the full 16-bit I/O address, allowing for 64 Kbytes of I/O addresses. Eight-bit I/O boards are also compatible with the ZT 8809A, provided the equivalent 8-bit addresses occupied by the on-board devices are avoided.
Getting Started FFFFh 0400h 03FFh Serial Port 1 (COM 1) 03F8h 03F7h 0380h 037Fh Printer Port 1 (LPT 1) 0378h 0377h 0300h 02FFh 02F8h 02F7h Serial Port 2 (COM 2) 0048h 0047h 0040h 003Fh 0028h 0027h 0020h 001Fh 8254 Timers 8259A Interrupt Controller 0000h Note: Shaded portion represents off-board I/O address space. Figure 2–5. I/O Map, STD DOS / STD ROM Systems.
Getting Started UPGRADING FROM ZT 8806/8807 SYSTEMS If you are upgrading your existing STD DOS system from ZT 8806/8807 boards to the ZT 8809A DOS systems, you should be aware of the enhancements introduced with the ZT 8809A DOS that may affect compatibility with existing systems. This section explains how the memory map and interrupt usage differ between the ZT 8809A systems and the ZT 8806 and ZT 8816 Revision A STD DOS systems.
Getting Started These changes affect the ZT 8844 EGA keyboard controller to the extent that the Revision A board is not compatible with the ZT 8809A DOS system. A modified version designated ZT 8844-III Rev. A, or ZT 8844 Rev. B or later, should be ordered with ZT 8809A DOS systems. If you are upgrading an existing system, contact Ziatech for upgrade charges and for a Return Material Authorization (RMA) number before returning the board. Note the upgraded ZT 8844-III Rev.
Chapter 3 THEORY OF OPERATION Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 RELATIVE MICROPROCESSOR PERFORMANCE . . . . . . . . . . . . . . . . 3-3 STD BUS COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 MEMORY AND I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 SERIAL COMMUNICATIONS . . . . . . . . . . . . . . . . . . .
Theory of Operation OVERVIEW This chapter describes the following system level issues: • Processor performance compared to the IBM PC/XT • STD bus compatibility • Serial communications using RS-232-C or RS-422/485 • Expanding the ZT 8809A interrupt structure • Direct Memory Access (DMA) support and benefits • Methods of battery backup with DC and AC power-fail detection • Battery life • Status indicator access (LED) • CMOS versions available for extended temperature and low power • Proc
Theory of Operation RELATIVE MICROPROCESSOR PERFORMANCE Norton’s System Information version 4.50 was used to measure the ZT 8808A and ZT 8809A processor performance relative to that of the IBM PC. The test compared several processing tasks; the test results are presented in Table 3-1. Table 3-1 Processor Speed Comparison. Test Computing Index (CI) Disk Index (DI) Performance Index (PI) Average Test Score Relative to 4.77 MHz PC ZT 8808A ZT 8809A 2.0 1.8 1.9 3.3 2.6 3.
Theory of Operation STD BUS COMPATIBILITY The ZT 8809A is fully compatible with Revision 2.3 of the STD-80 Series Bus Specification. This revision of the bus specification includes definition of two new backplane interrupt request signals, INTRQ1* and INTRQ2*, which replace the signals RESERVED and CNTRL*, respectively. (An asterisk indicates an active low signal.) Prior to ZT 8808 Revision 2.
Theory of Operation Serial Port 1 (COM1) The programming architecture of both serial ports 1 and 2 is the same as for the popular WD 8250. The baud rate generator is integral to the serial controller, configurable for a range of baud rates up to 56 Kbaud. All of the RS-232-C signals (TXD, RXD, CTS, RTS, DSR, and DTR) are implemented with RS-232-C drivers and receivers and are controlled by the registers within the serial port chip.
Theory of Operation Serial Port 2 (COM2) Serial ports 1 and 2 are identical in features and programming with respect to RS-232-C communication, with one exception. You can disable serial port 2 by removing jumper W66. This is useful for systems adding a modem card at the same I/O address as on the ZT 8809A. After removal of jumper W66, the ZT 8809A no longer reserves the I/O addresses 2F8 - 2FFh for the on-board serial port, and allows STD bus devices to reside here.
Theory of Operation Table 3-2 Serial Communications Standards. Parameter RS-232-C RS-423-A RS-422-A RS-485 Operation Single-ended Single-ended Differential Differential Number Of Drivers/Receivers 1/1 1/10 1/10 32/32 Maximum Cable Length (Ft.) 50 4000 4000 4000 20K 100K 10M 10M Maximum Data Rate † (Bits per second) † The ZT 8809A maximum data rate is limited to 56 Kbaud by the UART A terminated twisted pair should be used to protect the integrity of the RS-485 signals.
Theory of Operation INTERRUPTS The ZT 8809A supports both maskable and non-maskable interrupts. This section discusses system level issues related to these interrupts. Refer to Chapter 12 for more information on the operation and programming of the maskable interrupt controller. Interrupt Request Assignments The 8259A Programmable Interrupt Controller (PIC) on board the ZT 8809A has eight interrupt input requests, each with two possibilities for an interrupt source.
Theory of Operation Jumper Selections Interrupt Level W5 IR0 W4 IR1 W6 IR2 W7 IR3 W8 IR4 W2,W9 IR5 W3,W10 IR6 8087 Interrupt † Timer 0 † INTRQ1* FP1/ † INTRQ* Timer 2 FP3/ † COM2* Timer 1 † COM1* Power Fail/ †FP5/ INTRQ2* † FP6/ LPT1 † FP7/ W11 IR7 Figure 3–1. PIC Interrupt Input Requests.
Theory of Operation Polled Interrupts on the STD Bus The PIC can be programmed to supply a unique vector for each of these interrupt inputs. This means only one STD bus interrupt per request can be uniquely defined as shown in Figure 3-2. Since STD DOS expects the use of INTRQ1* and INTRQ2* for particular I/O devices, this leaves only the INTRQ* signal for all remaining I/O devices in the system.
Theory of Operation STD BUS INTERRUPT SOURCE 1 INTRQ* ISP INTRQ* INTAK* INTAK* ZT 8808A/ ZT 8809A INTERRUPT SOURCE 2 ISP INTRQ* INTAK* INTERRUPT SOURCE N ISP INTRQ* INTAK* INTERRUPT STATUS PORT Figure 3–2. Polled Interrupt Structure.
Theory of Operation STD Bus Vectored Interrupts For more demanding applications, it may be necessary to support each STD bus interrupt source with a unique vector, as illustrated in Figure 3-3. In this configuration, up to six STD bus interrupting devices can provide a unique vector for more efficient servicing than is possible by polling. This number may be decreased if STD DOS is present on the ZT 8809A.
Theory of Operation STD Bus Cascaded Interrupts To allow for a greater number of interrupts, additional interrupt controllers may be added to the STD bus system, allowing each interrupt source to generate a unique vector for its service routine. The ZT 8809A supports the STD-80 implementation of cascaded interrupt controllers, useful for demanding applications with a large number of interrupt sources. The system is illustrated in Figure 3-4.
Theory of Operation a unique vector. If STD DOS is installed, this number decreases depending upon the number of devices in the system. Non-Maskable Interrupts In addition to the eight interrupt inputs at the interrupt controller, the ZT 8809A supports three sources of interrupt referred to as "nonmaskable" interrupts (NMI). This type of interrupt has higher priority over any of the maskable interrupts from the interrupt controller and is not software maskable.
Theory of Operation DIRECT MEMORY ACCESS (DMA) The ZT 8809A supports Direct Memory Access (DMA) transfers between local memory and STD bus system memory or I/O under the supervision of an STD bus DMA controller. The following discussion covers system level issues of DMA transfers: the advantages and the operation of an STD bus DMA controller with respect to the CPU.
Theory of Operation DMA Operation Figure 3-5 shows the interface between the ZT 8809A and an STD bus DMA controller. The signals shown are required for proper operation of devices on the STD bus during DMA cycles. The DMA cycle is initiated when the controller asserts the bus request signal BUSRQ* on the STD bus. The ZT 8809A responds to this request by waiting for the CPU to finish the current instruction, then acknowledges the release of the bus by asserting the bus acknowledge signal BUSAK*.
Theory of Operation A0-A19 D0-D7 STD BUS I/O OR MEMORY WITH DMA BUSRQ* ZT 8808A/ ZT 8809A BUSAK* RD* WR* MEMRQ* MCSYNC* Figure 3–5. DMA With STD Bus Controller.
Theory of Operation POWER-FAIL PROTECTION The ZT 8809A supports both DC and AC power-fail protection. Advantages of each, as well as operation of both types of power-fail protection, are described in this section. DC Power-Fail The factory default setting enables the ZT 8809A to detect 5 VDC and assert a System Reset if power falls below 4.75 VDC. If the optional 3.9 V battery is installed, battery voltage switches in to protect those circuits selected by jumpers for battery backup.
Theory of Operation AC Power-Fail J5 ZT 90020 WALL TRANSFORMER All the logic required to detect AC power failure is present on the ZT 8809A except the AC converter. This converter is available from Ziatech as part number ZT 90071. One end of the converter plugs into the same AC source as the power supply to monitor AC to the STD system. The other end of the converter must be attached to connector J5 on the ZT 8809A, located at the frontplane near the extractor (see Figure 3-6). Figure 3–6.
Theory of Operation The advantage of AC power-fail detection is that it provides early warning of impending DC power failure. When jumper W1 is installed, a non-maskable interrupt (NMI) is sent to the processor when AC power below 95 VAC is detected. Alternatively, a maskable interrupt on level 5 (IR5) may indicate the AC power failure when jumper W1 is removed and W9A is installed. However, this indicator may not be seen if a higher priority interrupt is being serviced or interrupts are disabled.
Theory of Operation To detect AC power failure, the ZT 8809A may use any AC converter that provides transformer isolated AC voltage of no more than 30 VAC from the same source that provides power to the STD system. The detection circuitry on board the ZT 8809A is calibrated at the factory to generate an interrupt at 95 VAC RMS with the optional transformer available from Ziatech. If you use a different wall transformer, the following calibration sequence must be followed. 1.
Theory of Operation System Battery Fail For systems whose power is generated entirely from a large battery, the AC power-fail detection circuit may be useful to generate an early warning of battery failure. This warning should take place before the system battery voltage to the ZT 8809A falls below 4.75 V, at which time the system would reset. The values of R1 and R2 must be changed so the input voltage to the power monitor chip, the DS 1231-35, is above 2.5 V when power is good.
Theory of Operation BATTERY The ZT 8809A contains a socket for an optional 1 Amp-hour 3.9 V lithium battery. As described above, the real-time clock and 32 Kbyte static RAM are protected by the battery if jumper W12 is installed. Jumpers allow the RAM sockets and the configurable RAM/EPROM socket (when configured for RAM) also to be battery-backed. Jumper W35B battery backs the RAM sockets and W38A battery backs the RAM/EPROM socket.
Theory of Operation b) Minimum Data Retention Time: Total Current Drain = Clock + RAM + Buffer = 1 uA + 50 uA + 80 uA = 111 uA Battery Life = 1 AHr x 1 Day x 1 ------(24-8)Hr 111 uA = 563 Days (1.5 years) 2. Real-time clock, 32 Kbyte static RAM, one 128 Kbyte static RAM (monolithic part assumed) a) Typical Data Retention Time: Total Current Drain = Clock + RAM + Buffer + 128 Kbyte RAM = 1 uA + 1 uA + 8 uA + 1 uA = 11 uA Battery Life = 1 AHr x 1 Day x 1 ------(24-8)Hr 11 uA = 5896 Days (16.
Theory of Operation STATUS INDICATOR (LED) The ZT 8809A includes an LED near the extractor for general purpose use. It is turned on by writing a logical 1 to bit 1 of the printer port Control register at I/O address 037Ah, and is turned off by writing a logical 0 to bit 1 of the same address. This bit controls the printer port signal Autofeed (AFD), which is one of four signals at the printer interface shared between ZT 8809A uses and printer uses.
Theory of Operation RESET The ZT 8809A is equipped with a System Reset circuit that asserts the STD bus SYSRESET* signal at any time DC voltage is less than 4.75 V. It also drives the SYSRESET* signal during the time a pushbutton switch drives the PBRESET* STD bus signal to the ZT 8809A. The pushbutton switch is first debounced on the ZT 8809A before causing a system reset. The pushbutton must remain depressed a minimum of 0.5 microseconds for the debounce circuit to detect it properly.
Theory of Operation CMOS VERSIONS OF THE ZT 8808A/8809A The ZT 8808A and ZT 8809A processor boards are also available in CMOS versions, ZT 88CT08A and ZT 88CT09A, respectively. These versions provide lower power and extended temperature operation. Like the ZT 8808A and ZT 8809A, the ZT 88CT08A and ZT 88CT09A differ only in their processor clock speeds; they are 5 and 8 MHz, respectively.
Theory of Operation Clock Slowdown Power consumption for CMOS logic is directly proportional to the switching speed of the device. The higher the clock frequency, the greater the power dissipation. In order to minimize the power consumption on the ZT 88CT09A boards, the Clock Slowdown feature has been included to allow dynamic switching of the processor clock speed between the normal frequency and that frequency divided by 256. The ZT 88CT08A may be selected to run at either 5 MHz or 19.
Theory of Operation Halt with Interrupt Restart To further decrease power consumption from the Clock Slowdown mode described above, the processor clock may be halted during times processing is not needed, and restarted by an interrupt. This interrupt may be from an external source, such as an event requiring service from the processor, or from one of the on-board timers. Since the three 16-bit timers on board are driven by an independent oscillator, the timers continue to run at their full 1.
Chapter 4 APPLICATION EXAMPLES Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 EXAMPLE 1-A: USING SIMPLE INTERRUPTS . . . . . . . . . . . . . . . . . . . 4-3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Software Outline . . . . . . . . . . . .
Application Examples OVERVIEW The following examples show simple uses of some of the more complex devices on the ZT 8809A board. Each example is described first by an outline of the objectives, followed by the software in outline form.
Application Examples EXAMPLE 1-A: USING SIMPLE INTERRUPTS Objectives • Write a software routine that initializes the 8259A Interrupt Controller on board. • Initialize the pointer to the interrupt service routine for the interrupt used. • Provide the framework for an interrupt service routine. The example shown strobes the LED after a certain timeout interrupt provided by the timer 2.
Application Examples Software Outline INITPIC Routine BEGIN Initialize the Interrupt Controller Send ICW1 - Edge triggered, Single, ICW4 needed Send ICW2 - Vector addresses 8 - 15 Send ICW3 - No slave interrupt controllers Send ICW4 - SFNM, Buffered Master, Normal EOI, 8088 Send OCW1 - Unmask all interrupts for STD DOS use END Initialization of the Interrupt Vector BEGIN Initialize low memory with a pointer to the interrupt service routine (ISR) Write offset of ISR to lower word Write code segment to next
Application Examples LED_STROBE routine BEGIN Check state of LED Set it to the opposite state Send End of Interrupt (EOI) byte to PIC Return from ISR END INIT_TMR2 Routine BEGIN Send Control byte - set for Mode 2 as a Rate Generator Send low byte of count Send high byte of count END MAIN Program BEGIN Initialize the segment registers and stack Initialize the interrupt vector for the ISR Call INIT_PIC Call INIT_TMR2 Enable processor interrupts (already enabled if running on an STD DOS system) Go into an idl
Application Examples Program Code ; ;********************************************************** ;* * ;* PROGRAMMING ABSTRACT * ;* * ;********************************************************** ; ; SHAWN SHURICK ; 6/30/88 ; ZIATECH CORP. ; SAN LUIS OBISPO, CA ; ; THIS PROGRAMMING EXAMPLE IS FOR THE ZT 8809A CPU BOARD. ; IT IS INTENDED TO DEMONSTRATE THE USE OF THE 8259A ; INTERRUPT CONTROLLER TOGETHER WITH A COUNTER/TIMER.
Application Examples ; ;*********************************************************** ;* * ;* SYSTEM EQUATES * ;* * ;*********************************************************** ; ; * ZT 8809A 8259A REGISTER EQUATES BY PORT ADDRESS * ; ; REG A ICW,OCW2,OCW3,IRR,ISR,IL PORT_A_8809A EQU 0020H ; PORT_A ICW1_8809A EQU 00010001B ; EDGE, CASCADE OCW2_8809A EQU 01100010B ; SPECIFIC EOI FOR IR2 ; ; REG B ICW2,3,4,OCW1,IMR PORT_B_8809A EQU 0021H ; PORT B ICW2_8809A EQU 00001000B ; TYPES 8-15D ICW3_8809A EQU 00000000B ;
Application Examples ; ;*********************************************************** ;* * ;* MACRO DEFINITIONS * ;* * ;*********************************************************** ; GET MACRO SRC MOV DX,SRC ;; GET I/O PORT IN AL,DX ;; INPUT DATA ENDM ; PUT MACRO DST MOV DX,DST ;; GET I/O PORT OUT DX,AL ;; OUTPUT DATA ENDM ; ;*********************************************************** ;* * ;* INTERRUPT POINTERS SEGMENT * ;* * ;*********************************************************** ; ; INTERRUPT POINTER TA
Application Examples ;*********************************************************** ;* * ;* STACK SEGMENT * ;* * ;*********************************************************** ; ; STACK SEGMENT IS LOCATED IN RAM FOR AN ARBITRARY STACK ; SIZE.
Application Examples ;*********************************************************** ;* * ;* INTERRUPT HANDLERS * ;* * ;*********************************************************** ; ; ONLY ONE SERIAL INTERRUPT HANDLER IS ILLUSTRATED. OTHER ; HANDLERS CAN BE ADDED HERE AS NEEDED. ; CODE SEGMENT PARA ; ASSUME CS:CODE,SS:STACK,DS:DATA,ES:NOTHING ; LED_STROBE PROC ; ; THIS PROCEDURE HANDLES THE INTERRUPT GENERATED BY THE ; TIMER 2 ON THE ZT 8809A.
Application Examples ;*********************************************************** ;* * ;* PROCEDURES * ;* * ;*********************************************************** ; ; INIT_PIC PROC ; ; THIS PROCEDURE IS CALLED TO INITIALIZE THE 8259A PIC. ; THE PIC IS INITIALIZED TO: SINGLE MODE, EDGE TRIG; GERED, INTERRUPT TYPES 8 - 15 D FOR IRQS 0-7 RE; SPECTIVELY, 8088 MODE, NORMAL (NON-SPECIFIC) END; OF-INTERRUPT, IRQ LINES 0-7 ENABLED.
Application Examples ;*********************************************************** ;* * ;* TEST CODE * ;* * ;*********************************************************** ; ; INITIALIZE SEGMENT REGISTER AND STACK POINTER. ; START: MOV AX,SEG DATA MOV DS,AX MOV AX,SEG STACK MOV SS,AX MOV SP,OFFSET STACK_TOP ; ; INITIALIZE INTERRUPT VECTORS (TYPE 10 ONLY IS USED).
Application Examples EXAMPLE 1-B: HANDLING SLAVE INTERRUPTS Objectives • Write a software routine that initializes the 8259A Interrupt Controller on-board to act as a master to receive interrupts from both a slave interrupt controller and on-board devices. • Write a software routine that initializes the 8259A Interrupt Controller on the ZT 8840 Quad UART board to act as a slave interrupt controller.
Application Examples System Configuration The following example assumes that a ZT 8809A and a ZT 8840 are present in the STD bus card cage. All jumpers are assigned in the factory default configuration except the following: 1. ZT 8809A - No jumper changes required. 2. ZT 8840 - Remove jumpers W1 - W3 to assign the board to I/O address E0h.
Application Examples Initialize the 8840 Interrupt Controller Send ICW1 - Edge triggered, Cascade, ICW4 needed Send ICW2 - Vector addresses 248 - 255 D Send ICW3 - Slave interrupt controller ID #2 Send ICW4 - SFNM, Buffered Slave, Normal EOI, 8088 Send OCW1 - Unmask interrupt IR0 END INIT_VECT Routine BEGIN Initialize low memory with a pointer to the interrupt service routine (ISR) Write offset of ISR to lower word Write code segment to next higher word (This sequence would repeat for more than one ISR) EN
Application Examples SERIAL_8250 Routine BEGIN Indicate to the main program that the interrupt was received Disable further serial interrupts (no more are desired in this program) Send EOI to the ZT 8809A Send EOI to the ZT 8840 Interrupt Controller Return from Interrupt END MAIN Program BEGIN Initialize the segment registers and stack Use the routine to initialize the vector(s) Call INIT_UART Call INIT_PIC_8809A Call INIT_PIC-8840 Enable the interrupt inside the UART for transmit buffer empty Enable proce
Application Examples Program Code ; ;********************************************************** ;* * ;* PROGRAMMING ABSTRACT * ;* * ;********************************************************** ; ; SHAWN SHURICK ; 6/30/88 ; ZIATECH CORP. ; SAN LUIS OBISPO, CA ; ; THIS PROGRAMMING EXAMPLE IS FOR THE ZT 8809A CPU BOARD. ; IT IS INTENDED TO DEMONSTRATE THE USE OF THE 8259A ; INTERRUPT CONTROLLER TOGETHER WITH A COUNTER/TIMER.
Application Examples ; ;*********************************************************** ;* * ;* SYSTEM EQUATES * ;* * ;*********************************************************** ; ; ; EQU 0 ; SET TO 0 FOR STD DOS SYSTEM ; ; * ZT 8809A 8259A REGISTER EQUATES BY PORT ADDRESS * ; ; REG A ICW,OCW2,OCW3,IRR,ISR,IL PORT_A_8809A EQU 0020H ; PORT A ICW1_8809A EQU 00010001B ; EDGE, CASCADE, ICW4 NEEDED OCW2_8809A EQU 01100010B ; SPECIFIC EOI FOR IR2 ; ; REG B ICW2,3,4,OCW1,IMR PORT_B_8809A EQU 0021H ; PORT B ICW2_8809A
Application Examples ; PORT_INTEN PORT_DLAMB ERBI EIRBI EIRBO ELSI EDSSI ; ; PORT_INSTAT INTPND RVLNS RECDA TXHRE MODST ; ; PORT_LINEC WL5 WL6 WL7 WL8 STB PEN EPS SBK DLAB ; BD111 BD301 BD122 BD242 BD362 BD482 BD962 BD193 ; ; PORT_MODC DTR RTS OUT2 DIAG ; ; PORT_LINST DR ORE PE FE BKI THRE TSRE ; REG #1 INTERRUPT ENABLE REG (W) EQU 001H ; INTERRUPT EN. EQU 001H ; IF DLAB=1, MSB DIV.
Application Examples ; REG #6 MODEM STATUS REG (R) PORT_MODS EQU 006H ; MODEM STATUS DCTS EQU 01H ; DELTA CTS DDSR EQU 02H ; DELTA DSR TERI EQU 04H ; TRAIL RING IND. DSLSD EQU 08H ; DELTA RECV SIG. CTS EQU 10H ; CLEAR TO SEND DSR EQU 20H ; DATA SET READY RI EQU 40H ; RING INDICATOR RLSD EQU 80H ; RECV LINE DECT.
Application Examples TYPE_8 DD ? ; 8259A IR0-TIMER 0 TYPE_9 DD ? ; 8259A IR1-KEYBD TYPE_10 DD ? ; 8259A IR2-TIMER2 (W6B) TYPE_11 DD ? ; 8259A IR3-COM2 TYPE_12 DD ? ; 8259A IR4-COM1 TYPE_13 DD ? ; 8259A IR5-FP5 TYPE_14 DD ? ; 8259A IR6-FP6 TYPE_15 DD ? ; 8259A IR7-FP7 ; ; INTERRUPT POINTER TABLE IS LOCATED AT THE TOP END OF ; 256D INTERRUPT TYPES.
Application Examples ;*********************************************************** ;* * ;* INTERRUPT HANDLERS * ;* * ;*********************************************************** ; ; ONLY ONE SERIAL INTERRUPT HANDLER IS ILLUSTRATED. OTHER ; HANDLERS CAN BE ADDED HERE AS NEEDED. ; CODE SEGMENT PARA ; ASSUME CS:CODE,SS:STACK,DS:DATA,ES:NOTHING ; SERIAL_8250 PROC ; THIS PROCEDURE HANDLES INTERRUPTS GENERATED BY THE ; 8259A PIC ON THE ZT 8840.
Application Examples ;*********************************************************** ;* * ;* PROCEDURES * ;* * ;*********************************************************** ; ; INIT_PIC_8809A PROC ; ; THIS PROCEDURE IS CALLED TO INITIALIZE THE 8259A PIC. ; THE PIC IS INITIALIZED TO: SINGLE MODE, EDGE TRIG; GERED, INTERRUPT TYPES 8 - 15 D FOR IRQS 0-7 RE; SPECTIVELY, 8088 MODE, NORMAL (NON-SPECIFIC) END; OF-INTERRUPT, IRQ LINES 0-7 ENABLED.
Application Examples ; LED_STROBE PROC ; ; THIS PROCEDURE STROBES THE LED ON THE ZT 8809A, ; THEREBY INDICATING TO THE USER THE INTERRUPT EXPECTED WAS RECEIVED. ; FIRST THE PRINTER PORT BIT ; THAT CONTROLS THE LED IS READ AND EXTRACTED, THEN ; INVERTED AND OR’D BACK INTO THE BYTE READ. THE ; BYTE IS THEN REWRITTEN TO THE PRINTER PORT. THIS TAKES ; PLACE TWICE, SO THE LED IS PULSED EITHER ON OR OFF.
Application Examples INIT_UART PROC ; ; THIS PROCEDURE IS CALLED TO INITIALIZE A UART.
Application Examples ;*********************************************************** ;* * ;* TEST CODE * ;* * ;*********************************************************** ; ; INITIALIZE SEGMENT REGISTER AND STACK POINTER.
Application Examples ; MOV PUT STI MOV WAIT_RDY: IN AND JZ AL,EIRBO ; ENABLE DATA TRANSMIT ; INTERRUPT UART1+PORT_INTEN ; AT THE UART INTERRUPT ; ENABLE REG ; ENABLE INTERRUPTS DX,UART1+PORT_LINST ; GET CONSOLE STATUS AL,DX AL,THRE WAIT_RDY ; INPUT THE STATUS ; CHECK IT FOR TXMIT BUF EMPTY ; WAIT IF NOT EMPTY ; MOV PUT AL,0AAH ; PLACE A BYTE IN THE OUTREG UART1+PORT_XMT50 ; AGAIN: XOR WAIT_LP: LOOP CMP JNE CALL ; CODE CX,CX ; ZERO THE CX REG (MAX COUNT) WAIT_LP INT_FLAG,0 AGAIN LED_STROBE ; ; ;
Application Examples EXAMPLE 2: POWER-FAIL/WATCHDOG TIMER Objectives • Write routines for system initialization and system restart after power-fail. • Write a routine that handles the non-maskable interrupt that may be caused by power-fail. • Write a routine that handles the maskable interrupt from the watchdog timer timeout. • Determine in the main program whether system restart or system initialization is in process. Call the appropriate routine and execute it.
Application Examples System Requirements The following example assumes a ZT 8809A configured with the factory default jumper assignments, with the following exceptions. 1. 2.
Application Examples The following application example is written with both methods of power-fail detection in mind. The flowchart indicates that two different paths may be taken depending on whether the cause is an external battery failure or an AC power failure. If an external battery failure is being detected, it is assumed that the non-maskable interrupt remains until the battery is replaced, so the code goes into an idle loop awaiting battery change. System restart occurs with a new power-up.
Application Examples Software Outline MAIN Program BEGIN Point to battery-backed RAM (segment location DC00h for STD DOS) If "System Data Saved" flag set Then a "warm" start so call RESET routine Else A "cold" start so call INIT routine Remaining code to initialize the software and hardware (including 8259A PIC) that resides here END RESET Routine BEGIN Initialize the NMI routine pointer Restore the critical program data Restore the segment and scratchpad registers from battery-backed RAM Clear the "System
Application Examples INIT Routine BEGIN Initialize the NMI routine pointer Initialize the segment registers Initialize the software data Initialize the hardware, ie.
Application Examples If yes, halt the system, awaiting system battery replacement (for systems powered by battery only) If no, read SLIN* (bit 3) at the Printer Port Control register at address 037Ah. If set to 1, continue to read the bit and check. Power-fail condition persists. If set to 0, power-fail has resulted in a brownout condition, and the system did not need to stop (Vcc remained above 4.75 V). Call the RESET routine.
Application Examples Flowcharts For AC Power-Fail & Watchdog Interrupts MAIN PROGRAM START SET ES = BATTERY BACKED RAM (DC00h IS STD DOS DEFAULT) SYSTEM DATA SAVED FLAG SET? YES MUST BE A WARM START. CALL RESET ROUTINE NORMAL MAIN PROGRAM PROCEDES HERE WITH REMAINING APPLICATION SPECIFIC INITIALIZATION END 4-34 NO MUST BE A COLD START.
Application Examples RESET ROUTINE START INITIALIZE THE NMI INTERRUPT POINTER RESTORE CRITICAL PROGRAM DATA RESTORE PROGRAM SEGMENT REGISTERS TRIGGER THE WATCHDOG TIMER CLEAR THE SYSTEM DATA SAVED FLAG RETURN 4-35
Application Examples INIT ROUTINE START INITIALIZE THE NMI INTERRUPT POINTER INITIALIZE THE SEGMENT REGISTERS INITIALIZE THE SOFTWARE DATA INITIALIZE THE WATCHDOG TIMER USING ONE 8254 16-BIT TIMER SET TO MODE 4 INITIALIZE THE INTERRUPT CONTROLLER MASKING THE POWER FAIL INTERRUPT LEVEL 5 TRIGGER THE WATCHDOG TIMER RETURN 4-36
Application Examples NON-MASKABLE INTERRUPT SERVICE ROUTINE START TRIGGER THE WATCHDOG TIMER READ INTERRUPT REQUEST REGISTER BIT 5 IS IT SET? YES POWER FAIL NMI SO DO THE FOLLOWING NO OTHER NMI SO CHECK FOR SOURCES ELSEWHERE IN THE SYSTEM AND HANDLE THEM SAVE REGISTERS, IE, SEGMENT, AX, BX, CX, DX, SI, DI, BP, SP, IN BATTERY BACKED RAM SAVE CRITICAL PROGRAM DATA IN BATTERY BACKED RAM SET SYSTEM DATA SAVED FLAG IN BATTERY BACKED RAM, IE A PATTERN LIKE AA556996h 4-37
Application Examples IS POWER FAIL CIRCUIT USED TO DETECT LOW BATTERY SUPPLY VOLTAGE TO SYSTEM? NO AC POWER FAIL DETECTED SET SLIN BIT AT PRINTER PORT CONTROL REGISTER ADDRESS 037Ah TO 1 TO ALLOW READ (OPEN COLLECTOR OUTPUT) READ SLIN BIT AT PRINTER PORT CONTROL REGISTER ADDRESS 037Ah YES 4-38 IS IT SET TO 1? YES HALT PROCESSOR TO AWAIT MAIN BATTERY SUPPLY REPLACEMENT END
Application Examples NO THE POWER FAIL CONDITION IS ENDED IT MUST HAVE BEEN A BROWNOUT SITUATION WITH NO HARDWARE RESET REINITIALIZE THE INTERRUPT CONTROLLER TO CLEAR IRR CALL RESET ROUTINE RETURN FROM INTERRUPT END 4-39
Application Examples EXAMPLE 3: REAL-TIME CLOCK DRIVERS Objectives • Write the read and write routines which can initialize the time and read it back. • Write the real-time clock access routine, which is required before reading or writing the clock. System Configuration The ZT 8809A must be configured for the factory default jumper assignments for this example. It is assumed that STD DOS is not installed, since the clock is handled by STD DOS.
Application Examples END WRIT_CLK Routine BEGIN Write 64 bytes of data into the real-time clock Read the real-time clock once to reset the comparison register to be sure it is no longer accessible END MAIN Routine BEGIN Call INIT_CLK to be able to access the real-time clock Call WRIT_CLK to write the initial time to the clock (or) Call INIT_CLK to be able to access the real-time clock Call READ_CLK to read the clock and parse the data END 4-41
Chapter 5 MEMORY AND I/O CAPABILITY Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 MEMORY ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Memory Expansion (MEMEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 On-Board Memory Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Write Protection . . . . . . . . . . . . . .
Memory and I/O Capability MEMORY ADDRESSING The ZT 8809A processor board is capable of addressing up to 1 Mbyte of memory, both on-board and to the STD bus. This is the maximum memory addressing capability of the V20 and 8088 microprocessors. The upper four bits of the 20-bit memory address are multiplexed onto the STD bus data lines during address time. The remaining 16 address bits, along with memory request (MEMRQ*), are driven onto the 16 STD bus address lines during this time.
Memory and I/O Capability Also included on-board is a 32 Kbyte static RAM, referred to as the H: drive in STD DOS systems prior to BIOS Version 3.0 and the R: drive for BIOS versions of 3.0 and later. This RAM is located in the address space just below the EPROM on board. The memory address of this RAM varies with the EPROM sizes selected by jumpers W57-59. Write Protection A special feature is provided to protect the on-board static RAM from being over-written by errant applications code.
Memory and I/O Capability MEMORY MAPS Figures 5-1 through 5-6 represent some of the possible memory maps for the ZT 8809A, along with jumper configuration drawings. Figures 5-1 and 5-2 show the factory default configuration for an STD DOS system. In this example, one socket is used for a 256 Kbyte EPROM drive. Another socket is used for a 128 Kbyte EPROM drive, and the RAM sockets hold a total of 256 Kbytes to be used for system RAM.
Memory and I/O Capability TIMER COUNTER LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 128K RAM 128K RAM 256K EPROM W66 B A 128K EPROM W49 W68 A B W48 W47 B A A B W46 A B W37 ZT8809A REV. A W17 W18 W19 W20 W21 W22 W16 W12 W29 W30 W31 W32 W1 COM1 A W4 W5 W6 W7 W8 W9 W10 W11 W14 W3 A W15 B W2 A B W13 COM2 W23 W24 W25 W26 W27 W28 INTERRUPTS B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A A B W50 W60 W62 W63 W61 Figure 5–2.
Memory and I/O Capability Figures 5-3 and 5-4 also show an STD DOS system, with one 256 Kbyte EPROM drive and 640 Kbytes of system RAM. FFFFFh 256 Kbyte ROM Drive w/ 256 Kbyte EPROM DFFFFh D8000h C0000h BFFFFh 32 Kbyte RAM Drive and Timekeeper A0000h 9FFFFh 640 Kbytes on-board w/ a 128 Kbyte RAM in socket 3D1 and a 512 Kbyte RAM in socket 7D1 0h Note: Shaded portion represents off-board memory address space. Figure 5–3. STD DOS Map with 640K On-Board RAM.
Memory and I/O Capability TIMER COUNTER W12 W29 W30 W31 W32 LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 Not Installed 512K RAM 256K EPROM W66 B A 128K RAM W49 W68 A B W48 W47 B A A B W46 A B W37 ZT8809A REV. A W17 W18 W19 W20 W21 W22 W16 COM1 A W4 W5 W6 W7 W8 W9 W10 W11 W1 W14 W3 A W15 B W2 A B W13 COM2 W23 W24 W25 W26 W27 W28 INTERRUPTS B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A A B W50 W60 W62 W63 W61 Figure 5–4.
Memory and I/O Capability Figures 5-5 and 5-6 show the factory default configuration for nonDOS systems. Two of the sockets are configured to accept 64 Kbyte EPROMs, one for the STD ROM software and the other for a user EPROM. The other two sockets are configured for two 128 Kbyte RAMs for a total of 256 Kbytes of user RAM. This memory configuration might be used for an STD ROM system.
Memory and I/O Capability TIMER COUNTER W12 W29 W30 W31 W32 LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 32K SRAM B A STD ROM W49 W68 A B W48 W47 B A A B W46 A B W37 ZT8809A REV. A W17 W18 W19 W20 W21 W22 W16 COM1 A W4 W5 W6 W7 W8 W9 W10 W11 W1 W14 W3 A W15 B W2 A B W13 COM2 W23 W24 W25 W26 W27 W28 INTERRUPTS W66 B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A A B W50 W60 W62 W63 W61 Figure 5–6. Non-DOS Factory Default Jumper Configuration.
Memory and I/O Capability BATTERY BACKUP All on-board RAM may be battery-backed by a 3.9 V, 1 Amp-hour lithium battery installed on the ZT 8809A. The 32 Kbyte RAM drive and the real-time clock are always battery-backed if the battery is loaded and jumper W12 is installed (the factory default for ZT 8809A STD DOS systems). The two RAM sockets (7D1, 9D1) may select battery backup with jumper W35; the selectable RAM/EPROM socket (3D1) may select battery backup with jumper W38.
Memory and I/O Capability MEMORY DEVICE LOCATIONS Figure 5-7 shows the physical locations of the RAM and EPROM sockets on the ZT 8809A. Location 5D1 is the EPROM socket, locations 7D1 and 9D1 are the RAM sockets, and 3D1 is the RAM/EPROM selectable socket. 3D1 RAM/EPROM SELECTABLE SOCKET 5D1 EPROM SOCKET 7D1 RAM SOCKET 9D1 RAM SOCKET Figure 5–7. Memory Chip Locations.
Memory and I/O Capability Sockets 3D1 and 5D1 Sockets 3D1 and 5D1 as well as the battery-backed RAM are controlled primarily by jumpers W57-59. The eight possible memory configurations are shown in Table 5-1. Table 5-1 Memory Configurations, 3D1/5D1/BRAM.
Memory and I/O Capability Sockets 7D1 and 9D1 Sockets 7D1 and 9D1 are controlled primarily by jumpers W55 and W56. Table 5-2 shows the three possible memory configurations. Table 5-2 Memory Configurations, 7D1/9D1. Socket 7D1 1 2 3 00000-1FFFF (128K) 00000-7FFFF (512K) Disabled Socket 9D1 20000-3FFFF (128K) Disabled Disabled Note: Jumpers W67 and W68 affect the addressing of all of the sockets when W55 is installed and, concurrently, W56 is removed.
Memory and I/O Capability DEVICE ACCESS TIMES Table 5-3 shows the maximum chip select access times allowed by the ZT 8808A and ZT 8809A for on-board RAM and EPROM devices. Each device should be selected with a chip select access time less than this maximum. Table 5-3 Device Access Times.
Memory and I/O Capability INPUT/OUTPUT ADDRESSING The I/O addressability of the ZT 8809A is 64 Kbytes, equal to that of the V20 and 8088 series microprocessors. All 16 STD bus address lines are driven during I/O read or write cycles. The upper eight address lines remain at zero during 8-bit I/O instructions. All devices on-board are accessed with 16 bits of address. During on-board accesses, all address lines along with I/O Request (IORQ*) are driven to the backplane.
Memory and I/O Capability I/O Expansion (IOEXP) provides an additional address line for STD bus I/O boards, and may be jumpered to Vcc or ground via jumper W61. It is not dynamically driven by the ZT 8809A. Factory default ties IOEXP to ground.
Chapter 6 CPU DESCRIPTION (V20) Contents Page V20 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Program Counter (PC) [IP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Prefetch Pointer (PFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 General Purpose Registers . .
CPU Description V20 OVERVIEW The microprocessor on board the ZT 8809A is an NEC V20, which is an 8088 compatible microprocessor with a 16-bit internal and 8-bit external data bus. The V20 executes all code written for the 8088/8086 family of microprocessors and includes a superset of their instruction set. Mnemonics and execution times differ from those of the 8088/8086 family. Overall program execution will be faster in most cases.
CPU Description Each unit contains several registers important to the programmer. In the following description of these registers, the designator in brackets is the name of that register used by those who are familiar with the 8088 series of microprocessors. If no bracketed name is shown, no 8088 equivalent exists for this V20 register. Segment Registers The V20 can directly address up to one megabyte of memory in segments of 64 Kbytes or less.
CPU Description All memory addresses are specified by a segment and an offset. The 16-bit segment is shifted four binary digits to the left and added to the 16-bit offset to create the full 20-bit memory address. Table 6-1 shows the conventions established for the 8088 series microprocessors in using the available segment and offset registers for various types of memory accesses. The program always resides in a program segment pointed to by the PS [CS] register.
CPU Description Program variables generally reside in the data segment, referenced by the data segment 0 register (DS0) [DS]. The offset of each variable within the data segment is referenced by a result known as an effective address. The effective address is calculated from any combination of the displacement, base, and index registers. This provides for a large number of addressing modes. Strings are a special case of data references.
CPU Description Prefetch Pointer (PFP) This is a 16-bit binary counter. It contains the segment offset used to calculate a program memory address. The Bus Control Unit (BCU) uses this address to prefetch the next byte for the instruction queue. The contents of the PFP are an offset from the Program Segment (PS)[CS] register. The PFP is incremented each time the BCU prefetches an instruction from the program memory.
CPU Description Pointers and Index Registers These 16-bit registers serve as base pointers and index registers when accessing the memory using the based addressing, indexed addressing, or based indexed addressing modes. They can also be used for data transfer and for arithmetic and logical operations in the same manner as the general purpose registers. The base pointers are known as the BP and SP [BP and SP]. These are primarily used to reference the stack.
CPU Description Program Status Word (PSW) [FL] The program status word is a 16-bit register containing status and control flag information important to CPU and program operation. There are six status flags and four control flags whose bits are defined in Figure 6-1. Notice that some of the bits are not defined, but are reserved for future processor designs. The status flags provide information about the result of the previous arithmetic or logical processor operation.
CPU Description V20 ARCHITECTURAL ENHANCEMENTS This section focuses on the architectural enhancements that the V20 provides which improve its speed over that of the 8088 microprocessor.
CPU Description 16/32-Bit Temporary Shift Registers (TA,TB) Two 16-bit shift registers have been added for use by multiplication and division instructions, and for shift and rotate functions for temporary storage. These registers have decreased the execution time of multiplication and division instructions by a factor of four over the microprogramming method. If TA and TB are cascaded, they may be used as a 32-bit register useful for multiplication and division.
CPU Description Enhanced and Unique Instructions The V20 implements all of the 8088/8086 instructions. It also has a list of enhanced instructions as well as instructions unique to the V20.
CPU Description MODE OPERATIONS - 8080 EMULATION MODE Designs based on 8080 and 8085 microprocessors have two major limitations: not enough performance and lack of development tools. Upgrading an 8-bit design to a higher performance microprocessor requires time to convert the software. The V20 solves these problems by supporting two modes of operation: emulation and native. When the CPU is in native mode, it executes the 8088/8086 family of instructions along with the V20 enhanced and unique instructions.
CPU Description Figure 6-2 illustrates the possible modes of operation for the V20 processor and the methods used to transfer between them. HOLD REQ / HOLD ACK Native Mode 8088/86 Enhanced and Unique Instruction Set RESET, NMI or INT and IE HALT RETEM BRKEM RETI INT and ID Idle at 10% Power CALLN INT or NMI RESET HLT 8080 Emulation Standby Mode HOLD REQ / HOLD ACK 8080 MODE Figure 6–2. V20 Modes.
CPU Description Break for Emulation (BRKEM) This is the basic instruction used to start the 8080 emulation mode. This instruction operates identically to the software interrupt instruction BRK [INT], except it resets the mode flag MD to 0 in the PSW [FL]. The PSW, PS, and PC [FL, CS, and IP] registers are pushed onto the stack. The MD flag is then reset, and the interrupt vector specified by the immediate operand in this instruction is loaded into the PS and PC [CS and IP].
CPU Description Call Native Routine (CALLN) The CALLN instruction makes it possible to call native mode subroutines when in emulation mode. The processing steps taken by this instruction are similar in 8080 code to those taken by the BRK [INT] instruction in 8088/8086 code. The 8-bit immediate operand of this instruction specifies an interrupt vector type, which is then multiplied (shifted left 2 bits) by four to create an address.
CPU Description Register Use in Emulation Mode Register names for the 8080 processor differ from those of the V20. The V20 registers must therefore consistently take the place of corresponding 8080 registers during emulation mode. These register uses are defined in Table 6-2. Table 6-2 8080 Emulation Register Use.
CPU Description Keep in mind that the use of independent stack pointers in emulation mode allows independent stack areas to be secured for each mode, which keeps the stack of one of the modes from being destroyed by an erroneous stack operation in the other mode. The SP, IX, IY, and AH registers and the four segment registers PS, SS, DS0, and DS1 used in the native mode are not affected by operations in 8080 emulation mode.
CPU Description DMA SUPPORT The STD-80 Series Bus Specification defines two signals used by processor boards and DMA devices to exchange control of the STD bus for DMA transfers. These two signals are Bus Request (BUSRQ*) and Bus Acknowledge (BUSAK*), pins 42 and 41 on the STD bus, respectively. Use of DMA increases data transfer speeds from one device to another, frees the processor for other tasks while the transfer takes place, and may significantly increase system throughput.
CPU Description Figure 6-3 illustrates the signals required for a transfer between an STD bus DMA controller and the ZT 8809A. A0-A19 D0-D7 STD BUS I/O OR MEMORY WITH DMA BUSRQ* ZT 8808A/ ZT 8809A BUSAK* RD* WR* MEMRQ* MCSYNC* Figure 6–3. DMA With STD Bus Controller.
CPU Description RESET STATE The ZT 8809A contains on-board power-fail detection logic that detects DC, and optionally AC, power failure. This topic is covered more fully in Chapter 13. The DC power failure mechanism is used to detect a valid Vcc level and assert reset to the STD system for approximately 600 milliseconds after that time. Reset to the system is sent on the STD bus via the SYSRESET* signal, pin 47.
CPU Description WAIT-STATE GENERATOR The ZT 8809A contains a one wait-state generator for use with slower memory and I/O boards, to allow for an increase in the memory and I/O access time. The V20 processor extends the four-clock memory and I/O cycles to five clocks when one wait state is requested at its READY input. Proper selection of jumper W36 chooses between zero (W36A) and one (W36B) wait state.
Chapter 7 NUMERIC DATA PROCESSOR (8087) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 ZSBC 337 PIGGYBACK PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 INSTALLING THE ZSBC 337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 COPROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 MEMORY ADDRESSING . . . . . . . . . . . . . . .
Numeric Data Processor (8087) The 8087 offers numeric data formats and arithmetic operations that conform to the IEEE Microprocessor Floating Point Standard. All the proposed IEEE floating point algorithms, exception detection and handling, infinity arithmetic, and rounding controls are implemented. The 8087 typically offers a hundredfold improvement in throughput over calculations done entirely in software routines executed by the V20.
Numeric Data Processor (8087) zSBC 337 PIGGYBACK PROCESSOR The large number of memory sockets on the ZT 8809A necessitates the use of Ziatech’s zSBC piggyback processor option if the 8087 is desired. This 2" x 2" card serves to extend board space by housing the V20 microprocessor chip and the 8087 coprocessor chip beside one another. The base of the zSBC 337 has a 40-pin dual inline socket that provides elevation from the ZT 8809A.
Numeric Data Processor (8087) WARNING! The following procedure must be done at a static-free workstation to avoid damage to the V20 or 8087 components. INSTALLING THE zSBC 337 1. Carefully remove the V20 microprocessor chip from the ZT 8809A while in a static-free workstation. Immediately install the V20 to the assigned location on the zSBC 337 piggyback board. 2. Remove jumper W54 on the ZT 8809A to enable the 8087. 3.
Numeric Data Processor (8087) 5. For added mechanical support of the zSBC 337 module, an optional spacer may be added between the module and the ZT 8809A board. This spacer aligns vertically between a tooling hole in the corner of the module and a mounting hole on the ZT 8809A. These holes accept a #3 screw or smaller to be inserted through the spacer. Suggested part numbers include: a) Spacer - 7/16" or 9/16" spacer x .
Numeric Data Processor (8087) 6. Refer to Figure 7-1 for an illustration of the zSBC 337 installation. Note: If you install a hybrid version of the 128 Kbyte RAM in socket 3D1 (the memory socket under the zSBC 337 module), an extra spacer socket may be required. Ziatech recommends the 40-pin collet socket made by Augat, part number 540-AG19D. This configuration also requires insertion of an extra spacer pin between the zSBC 337 P2-2 and the ZT 8809A J7 pin 2. Figure 7–1.
Numeric Data Processor (8087) COPROCESSOR INTERFACE Communication between the 8087 and the V20 occurs over the request/grant, queue-status, and busy lines. The 8087 uses the request/grant line to obtain control of the local bus for data transfers. The request/grant sequence is as follows: 1. A pulse, one clock wide, is passed to the CPU to indicate a local bus request by the 8087. 2. The 8087 waits for the grant pulse. When received, the 8087 initiates a bus transfer in the following clock cycle. 3.
Numeric Data Processor (8087) The 8087’s busy signal informs the V20 that the 8087 is executing an instruction. It is connected to the V20 POLL/[8088 TEST] pin to provide synchronization via the V20 WAIT instruction in the case where the V20 must wait for an 8087 result before the V20 continues with subsequent instructions. MEMORY ADDRESSING The 8087 has seven different memory operand formats. Six of them are longer than one 16-bit word.
Numeric Data Processor (8087) INTERRUPT/NUMERIC ERRORS Two courses of action are possible when a numeric error occurs: The NDP can handle the error itself, allowing numeric program execution to continue undisturbed; or host software can manage it. In order to have the 8087 handle a numeric error, set its associated mask bit in the NDP control word. Each numeric error may be individually masked. The NDP has a default fixup action defined for all possible numeric errors when they are masked.
Numeric Data Processor (8087) Some very simple applications may mask all of the numeric errors. In this simple case, the 8087 interrupt request (INT) signal may be left unconnected since the 8087 never asserts this signal. If any numeric errors are detected during the course of executing the program, the NDP generates a safe result. It is sufficient to test the final result of the calculation to see if it is valid.
Numeric Data Processor (8087) No 8087 interrupts All errors on the 8087 are always masked. Numeric interrupts are not possible. Leave the 8087 INT signal unconnected. Single interrupt system The 8087 is the only interrupt in the system. Connect the 8087 INT signal directly to the interrupt request 0 (IR0) at the 8259A Programmable Interrupt Controller (PIC) via jumper W5A. Alternatively, tie the INT signal to the Non-Maskable Interrupt (NMI) request via jumper W51.
Numeric Data Processor (8087) Use the lowest priority interrupt input to the interrupt controller for the 8087, which is IR7 at the PIC. This requires wire-wrapping the 8087 INT to IR7. Refer to Chapter 12 for further information regarding the interrupt controller. The 8087 interrupt handler should allow further interrupts by higher priority events.
Numeric Data Processor (8087) REFERENCES – Cooner, Jerome, "An Implementation Guide to a Proposed Standard for Floating Point," Computer, Institute of Electrical and Electronic Engineers, Jan. 1980. – Palmer, John, & Wymore, Charles, "Making Mainframe Mathematics Accessible to MicroComputers," Electronics, 8 May 1982. (or AR-135 from Intel Corporation) – Rash, Bill, "Getting Started with the Numeric Data Processor," Intel Corporation. – The 8087 User’s Manual Numerics Supplement, Corporation.
Chapter 8 SERIAL COMMUNICATIONS (16C452) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 SERIAL COMMUNICATIONS PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 8-3 SERIAL INTERFACE (RS-232-C/422/485) . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 RS-232-C vs. RS-422/485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Signal Definitions . . . . . . . . . . . . . . . . . . . . . .
Serial Communications (16C452) OVERVIEW This chapter describes the two 16C450-equivalent serial ports available on the ZT 8809A. They are referred to as COM1 and COM2 in STD DOS systems and ports 1 and 2 in non-DOS systems. These two serial ports are contained within the VL 16C452 Communications Element from VLSI Technologies. The first section of this chapter details an overview of the software communications priority scheme, with a basic outline of the protocol between two serial devices.
Serial Communications (16C452) SERIAL COMMUNICATIONS PROTOCOL The following paragraphs describe the functioning of a serial data link between the ZT 8809A and a terminal or other computer. The ZT 8809A is shipped configured as Data Communications Equipment (DCE) for both serial ports 1 and 2. DCE is usually a device such as a modem that would talk to a computer like a PC through the PC’s COM1 port.
Serial Communications (16C452) In the transmit loop, CTS is tested until set, indicating that the other device is ready to receive data. CTS occurs when the transmitter-to-be sends RTS, asking the receiver-to-be to prepare to receive. The transmit loop starts by asserting RTS, telling the other device to prepare to receive. The other device signals it is okay to transmit by asserting CTS. The RTS line on the ZT 8809A is asserted by writing to the Modem Control register, setting bit 1.
Serial Communications (16C452) Data Communications Equipmnent (DCE) ZT 8808A/8809A COM 2 POWER-UP Do I xmit?† no Data Terminal Equipment (DTE) OTHER POWER-UP yes Assert RST Is CTS set? yes Do I xmit?† no Assert RST Is CTS set? no Assert RTS Is CTS set? Recv byte Xmit byte no no no Assert RTS Is CTS set? Recv byte Xmit byte no no Last byte? Last byte? De-assert RTS Last byte? Last byte? De-assert RTS TXD RXD TXD RXD RTS CTS ZT 8808A/8809A J2 GND RTS CTS USER GND †A communicatio
Serial Communications (16C452) The ZT 8809A COM1 and COM2 are shipped configured as DCE. However, if the opposite configuration is desired for either of these ports, see Appendix A for the required jumper configurations. If you prefer to use only a "three-wire" serial interface (that is, TXD, RXD, and ground), the ZT 8809A can be used without the RTS and CTS lines. Both serial devices appear to be always ready to transmit and receive.
J1 Note: dotted lines represent loopback of these signals at the external device. ZT 8809A REV A W28 W27 W26 W25 W24 W22 W21 W20 W32 B A W19 W18 W23 B A W17 W31 W30 W29 B A Wire wrap to loop back DTR to DSR on COM1. Wire wrap to loop back RTS to CTS on COM1. Wire wrap to loop back DTR to DSR on COM2. Wire wrap to loop back RTS to CTS on COM2. Serial Communications (16C452) Figure 8–2. Loopback of RTS/CTS, DTR/DSR.
Serial Communications (16C452) SERIAL INTERFACE (RS-232-C/422/485) The ZT 8809A provides two high-speed RS-232-C serial ports. These use the same programming architecture and pin definitions as the popular 8250 from Western Digital. The serial ports are contained within the 16C452 Communications Element. Serial port 1 (COM1) is dedicated for RS-232-C operation, whereas serial port 2 (COM2) is jumper selectable between RS-232-C or RS-422/485 operation.
Serial Communications (16C452) INTERNAL DATA BUS D7-D0 DATA BUS BUFFER RECEIVER BUFFER REGISTER RECEIVER SHIFT REGISTER LINE CONTROL REGISTER RECEIVER TIMING & CONTROL SIN DIVISOR LATCH (LS) DIVISOR LATCH (MS) A0 A1 A2 CS0 CS1 CS2 SELECT & CONTROL LOGIC AIOR BAUD GENERATOR LINE STATUS REGISTER TRANSMITTER TIMING & CONTROL TRANSMITTER HOLDING REGISTER TRANSMITTER SHIFT REGISTER SOUT IOWC MODEM CONTROL REGISTER CLK MODEM CONTROL LOGIC MODEM STATUS REGISTER POWER SUPPLY +5V GND RTS CTS D
Serial Communications (16C452) The ZT 8809A provides fully buffered RS-232-C serial data and control lines via two connectors, supplying the ±12 V swing needed to meet RS-232-C driver requirements. In addition, RS-422/485 drivers are on board, available for use at COM2. Refer to Appendix A for the proper jumper selections. The RS-232-C buffers meet the RS-232-C standard for signal conditioning for the recommended 50-foot cables.
Serial Communications (16C452) Signal Definitions The following is a description of each of the 16C452 signal inputs and outputs in the signal name. The 0 (zero) refers to serial port 1 (COM1) and the 1 (one) to serial port 2 (COM2). Clear-To-Send Inputs (CTS0*, CTS1*) The logical state of each CTS* pin is reflected in the CTS bit of the Modem Status register (MSR), bit 4.
Serial Communications (16C452) Data-Terminal-Ready (DTR0*, DTR1*) Each DTR* pin can be set active (low) by writing a logical 1 to the DTR bit in the Modem Control register (MCR), bit 0, of its associated UART. This signal is cleared (high) by writing a logical 0 to the DTR bit in the MCR or whenever a reset occurs. When active, the DTR* pin indicates that its UART is ready to receive data.
Serial Communications (16C452) Ring Indicator Inputs (RI0*, RI1*) When active (low), RI* indicates that a telephone ringing signal has been received by the modem or data set. The RI* signal is a modem control input whose condition is tested by reading the RI*, bit 6, of the associated UART’s MSR. The MSR output bit TERI, bit 2, indicates whether the RI* input has changed from high to low since the previous reading of the same MSR.
Serial Communications (16C452) Reset Control (RESET*) The ZT 8809A contains power-up and pushbutton reset circuitry that drives the RESET* input signal at the serial ports. The reset forces the serial ports into an idle mode in which all serial data activities are suspended. The Modem Control register (MCR) and its associated outputs are cleared. The Line Status register (LSR) is cleared except for the THRE and TEMT bits, which are set.
Serial Communications (16C452) Request-To-Send (RTS0*, RTS1*) The RTS* pin is set active (low) by writing a logical 1 to bit 1 of the associated UART’s Modem Control register. Both RTS* pins are disabled (set high) by reset. The RTS* signal on each UART is used to enable the modem. When active, an RTS* pin indicates that its UART has data ready to transmit. In half-duplex operations, RTS* is used to control the direction of the line.
Serial Communications (16C452) SERIAL REGISTERS This section describes the individual UART registers. You may access or control any of the serial registers summarized in Table 8-3 on page 8-18. The registers are used to control the serial ports’ operation and to transmit or receive data. There is a complete set of these registers for each UART. The base I/O address of each UART is 03F8h for serial port 1 (COM1) and 02F8h for serial port 2 (COM2).
Serial Communications (16C452) Table 8-2 ZT 8809A I/O Port Assignments. I/O Port Base + I/O Address I/O Read Register I/O Write Register 0 1 2 3 4 5 6 7 3F8h 3F9h 3FAh 3FBh 3FCh 3FDh 3FEh 3FFh Data Buffer Ch1 Intr. Enable Ch1 Intr. Indent. Ch1 Line Control Ch1 Modem Cntrl. Ch1 Line Status Ch1 Modem Status Ch1 --- Data Buffer Ch1 Intr. Enable Ch1 --Line Control Ch1 Modem Cntrl. Ch1 Line Status Ch1 ----- 0 1 2 3 4 5 6 7 2F8h 2F9h 2FAh 2FBh 2FCh 2FDh 2FEh 2FFh Data Buffer Ch2 Intr. Enable Ch2 Intr.
Serial Communications (16C452) Table 8-3 16C452 Addressable Registers Summary. Register Address 0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 3 Bit Interrupt IdenNo.
Serial Communications (16C452) Table 8-3 16C452 Addressable Registers Summary (continued).
Serial Communications (16C452) Transmit and Receive Buffer Registers The Transmitter Buffer register and Receiver Buffer register are data registers holding from five to eight bits of data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted.
Serial Communications (16C452) Line Control Register (2FBh, 3FBh; R/W) Use the Line Control register (LCR) to specify the format of the asynchronous data communications exchange. In addition to controlling the format, you may retrieve the contents of the Line Control register for inspection. This feature simplifies system programming and eliminates the need for storing line characteristics in system memory. Contents of the LCR are included in Table 8-3 on page 8-18 and are described below.
Serial Communications (16C452) Bit 2 Bit 2 specifies the number of stop bits in the transmitted or received serial character. If bit 2 is a logical 0, one stop bit is generated or checked in the transmit or receive data, respectively. If bit 2 is a logical 1 when a 5-bit word length is selected via bits 0 and 1, 11⁄2 stop bits are generated or checked. If bit 2 is a logical 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated or checked.
Serial Communications (16C452) Bit 6 This is the Set Break Control bit. When bit 6 is a logical 1, the serial output (SOUT) is forced to the spacing (logical 0) state until reset by a low-level bit 6, regardless of other transmitter activity. This allows the CPU to alert a terminal in a computer communications system and has no effect on the transmitter logic. If the following sequence is used, no erroneous or extraneous characters are transmitted because of the break. 1.
Serial Communications (16C452) Baud Rate Generator The serial baud rate generator takes the clock input (1.8432 MHz) and divides it by any divisor from 1 to 65,536. The output frequency of the baud generator is 16 times the baud rate. Two 8-bit latches store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization in order to ensure desired operation of the baud rate generator.
Serial Communications (16C452) Table 8-4 Baud Rate Table. Baud Rates Using 1.8432 MHz Clock (F) Baud Rate (B) Divisor (D) 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 % Error 0.026 0.058 .69 2.
Serial Communications (16C452) Line Status Register (2FDh, 3FDh; R/W) This 8-bit register provides status information to the CPU concerning the data transfer. Reading the Line Status register (LSR) clears bits 1 through 4 (OE, PE, FE, and BI). The contents of the LSR are included in Table 8-3 on pages 8-18 and 8-19, and a description follows. Bit 0 This bit is the receiver Data Ready (DR) indicator.
Serial Communications (16C452) Bit 4 This bit is the Break Interrupt (BI) indicator. Bit 4 is set to logical 1 whenever the received data input is held in the spacing (Logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: Bits 1 through 4 of the LSR are the error conditions that produce a Receiver Line Status interrupt whenever any of the corresponding conditions are detected.
Serial Communications (16C452) Interrupt ID Register (2FAh, 3FAh; R) The Interrupt Identification register (IIR) stores an identification code or "ID" of pending interrupts. In order to provide minimum software overhead during data character transfers, the serial hardware prioritizes interrupts into four levels: Receiver Line Status (priority 1), Received Data Ready (priority 2), Transmitter Holding Register Empty (priority 3), and Modem Status (priority 4). Refer to Table 8-5 below.
Serial Communications (16C452) Information stored in the IIR indicates that a prioritized interrupt is pending. The source of the interrupt is also indicated. The IIR, when addressed during chip-select time, freezes the highest priority interrupt pending, and no other interrupts are acknowledged until the particular interrupt is serviced by the CPU. The contents of the IIR are indicated in Table 8-3 on pages 8-18 and 8-19 and are described below.
Serial Communications (16C452) Interrupt Enable Register (2F9h, 3F9h; R/W) The Interrupt Enable register (IER) enables the four interrupt sources of the serial interface to separately activate the on-board interrupt hardware. It is possible to totally disable the interrupt system by resetting bits 0-3 of the IER. Similarly, by setting the appropriate bits of this register to logical 1, selected interrupts can be enabled.
Serial Communications (16C452) Modem Control Register (2FCh, 3FCh; R/W) The Modem Control register (MCR) controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the MCR are included in Table 8-3 on pages 8-18 and 8-19 and are described below. The RTS* and DTR* outputs are directly controlled by their control bits in this register. A high written to these bits asserts the signal active (low) at the output.
Serial Communications (16C452) Bit 4 This bit provides a loopback feature for diagnostic testing of the 16C452.
Serial Communications (16C452) Modem Status Register (2FEh, 3FEh; R) The Modem Status register (MSR) provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to this current-state information, four bits of the MSR provide change information. These bits are set to logical 1 whenever a control input from the modem changes state. They are reset to logical 0 whenever the CPU reads the MSR.
Serial Communications (16C452) Bit 5 This bit is the complement of the Data-Set-Ready (DSR*) input. When set, this bit indicates that the modem is ready to provide received data to the serial channel receiver circuitry. When DSR* is active (low), this bit is set to 1. If the channel is in the loopback mode, this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (RI*) input. If the channel is in the loopback mode, this bit doesn’t reflect any MCR bit status.
Chapter 9 CENTRONICS PRINTER INTERFACE Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 PRINTER PORT OUTPUT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . 9-3 USING THE PRINTER PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 REGISTER DEFINITIONS/ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Centronics Printer Interface The printer interface is a bidirectional parallel data port that fully supports the parallel Centronics type printer. This parallel port may be used either for basic I/O or for a printer. It consists of eight I/O lines for data, four open-collector I/O lines for control, and five input lines for status. These signal groups are available at the Data Port, Control Port, and Status Port registers, respectively. The open-collector lines have internal 2.5 kΩ pullups to +5 V.
Centronics Printer Interface PRINTER PORT OUTPUT CHARACTERISTICS The current drive capabilities of the 16C452 printer port signals are tabulated below in Table 9-1. Table 9-1 16C452 Printer Port Output Characteristics. OUTPUTS Signal IOL (mA) IOH (mA) PD0-7 INIT*,AFD*,STB*,SLIN* 12.0 10.0 -2.0 -0.
Centronics Printer Interface USING THE PRINTER PORT Physical access to the printer port may be gained through connector J6, a 20-pin header located behind connectors J2 and J3 at the frontplane. An optional cable, the ZT 90039, is available from Ziatech for transition from this 20-pin header to a 25-pin D-type connector similar to that used by IBM for their printer cable. Connection to a printer may be made by attaching the ZT 90039 to the IBM cable, which then connects to the printer.
Centronics Printer Interface REGISTER DEFINITIONS/ADDRESSES Printer Port registers are accessed at I/O addresses 0378h through 037Ah, with 037Bh unused. I/O addresses 037Ch through 037Fh redundantly map addresses 0378h to 037Bh, respectively. Tables 9-2 and 9-3 show register definitions and corresponding addresses. Table 9-2 Parallel Port Register Definitions.
Centronics Printer Interface Data Port The Data Port register is an 8-bit bidirectional register with an output control signal LPTOE* at connector J6, pin 10. When LPTOE* is active (low), the Data Port is an output port; when LPTOE* is inactive (high), the Data Port is an input port. There is a 470 Ω pulldown resistor on LPTOE* to bring it low when it is not driven at connector J6, making it an output port.
Centronics Printer Interface Status Port The Status Port register has five read-only status bits: 1. Busy (BUSY) 2. Acknowledge (ACK*) 3. Paper Error (PE) 4. Printer Selected (SLCT) 5. Error (ERROR*) None of these bits in the Status Port register are inverted from connector J6, with the exception of the BUSY signal. This is not immediately obvious from the signal names, of which ACK* and ERROR* show an active low state.
Centronics Printer Interface Control Port The Control Port register has four input/output signals: 1. Select In (SLIN*) 2. Initialize (INIT*) 3. Autofeed (AFD*) 4. Strobe (STB*) The Control Port register also contains an interrupt request enable bit, IRQ ENB, which is an internal control signal. All I/O signals are inverted at the frontplane except INIT*.
Centronics Printer Interface Interrupt Capability Set IRQ ENB to logical 1 to enable the interrupt from the printer port. Set IRQ ENB to 0 to disable the interrupt from the printer port. The interrupt is generated when the ACK* signal goes inactive (high) and is a result of the rising edge of ACK*. Therefore, if ACK* remains high, no further interrupts are generated. For STD DOS use, the IRQ ENB bit is set to 0, since STD DOS does not use the printer port interrupt.
Centronics Printer Interface Shared Signals Four printer port signals on the ZT 8809A (INIT*, AFD*, ERR*, and SLIN*) are shared by various logic functions. Initialize (INIT*) is used to control the RS-485 drivers and is needed for this control function only if multiple drivers are present on the RS-485 bus. If the ZT 8809A is to be a receiver or transmitter only, the RS-485 drivers may be disabled or enabled via hardware jumpers. In this case, INIT control is not needed and W13B is removed.
Centronics Printer Interface Select In (SLIN*) is used for SLOW/FAST control, to allow the software to dynamically control the processor clock frequency to conserve power in low-power CMOS applications. Processor clock speed is switchable between 19.5 kHz and 5 MHz for the ZT 88CT08A and 31.25 kHz and 8 MHz for the ZT 88CT09A, provided W46B is installed. If SLIN* is needed for the printer, the processor speed may then be controlled by jumpers W46A and B.
Centronics Printer Interface DISABLING SHARING OF PRINTER PORT SIGNALS This section describes how to dedicate the shared printer port signals to printer use only. All four shared signals (INIT*, AFD*, ERR*, and SLIN*) are treated as a group by STD DOS, so if only one is needed by the printer, all four are still made available. If you are not using STD DOS, each signal may be individually selected for I/O or printer purposes by jumper selections as described in Appendix A.
Centronics Printer Interface 3. Finally, modify the ZT 90039 printer cable. If you are using STD DOS, all four signals (AFD*, ERROR*, INIT*, and SLIN*) must be soldered to pins 14 through 17 in the 25-pin D-type connector. You may also order an alternative cable, the ZT 90074. It connects all four signals within the D-type connector’s backshell.
Centronics Printer Interface OPTIONAL PRINTER CABLE PINOUT Table 9-5 below defines the pinout for the ZT 90039 printer port cable, including the frontplane connector J6 pin definitions and the corresponding pin on the ZT 90039 25-pin D-type connector, which is identical to the IBM 25-pin D-type connector pinout. Note: An alternative cable, the ZT 90074, should be used if the shared signals are needed by the printer. The pinout is identical except all signals are connected. Table 9-5 ZT 90039 Cable Pinout.
Centronics Printer Interface PRINTER PORT RESET STATE The system reset signal does not affect the printer port inside the VL 16C452. Following a power-up or pushbutton reset, the Data and Control Ports initially assume a random state. The Status Port is an input port and always reflects the state at the input pins, including at power-on time.
Chapter 10 REAL-TIME CLOCK (DS 1215) Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMECHIP COMPARISON REGISTER DEFINITION . . . . . . . . . . . . . TIMEKEEPER REGISTER INFORMATION . . . . . . . . . . . . . . . . . . . . . . TIMECHIP REGISTER DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock (DS 1215) The memory management portion provides the necessary support circuitry to prevent an invalid chip access to a RAM when power is failing. The timekeeper shares memory address space with a batterybacked RAM, known as the RAM drive in STD DOS systems. Wherever this RAM is located in system address space, according to jumpers W57-59, the real-time clock may be addressed there as well. Factory default is D8000h.
Real-Time Clock (DS 1215) OPERATION To access the real-time clock in an STD DOS system, use the DOS functions "Time" and "Date" when at the DOS command line, or use interrupt 1Ah function 2 to get to the real-time clock when running an application program. STD DOS keeps a software clock for its own time and date, which saves time in accessing the real-time clock on board.
Real-Time Clock (DS 1215) Next, the 64-bit signature must be sent to the timekeeper by executing 64 consecutive write cycles containing the proper data on data bit 0, the least significant bit of the data bus. The proper data is illustrated in Figure 10-2 and is listed here in hex values: C5, 3A, A3, 5C, C5, 3A, A3, 5C. All accesses prior to recognition of the 64-bit pattern are directed to the RAM.
Real-Time Clock (DS 1215) TIMECHIP COMPARISON REGISTER DEFINITION 7 6 5 4 Byte 0 1 1 0 0 Byte 1 0 0 1 Byte 2 1 0 Byte 3 0 Byte 4 3 2 1 0 1 0 1 C5 1 1 0 1 0 3A 1 0 0 0 1 1 A3 1 0 1 1 1 0 0 5C 1 1 0 0 0 1 0 1 C5 Byte 5 0 0 1 1 1 0 1 0 3A Byte 6 1 0 1 0 0 0 1 1 A3 Byte 7 0 1 0 1 1 1 0 0 5C 0 Figure 10–2. Timechip Comparison Register.
Real-Time Clock (DS 1215) TIMEKEEPER REGISTER INFORMATION Timekeeper information is contained in eight registers of 8 bits each that are sequentially accessed one bit at a time after the 64-bit pattern recognition sequence is completed. When updating the timekeeper registers, each must be handled in groups of eight bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 10-3.
Real-Time Clock (DS 1215) TIMECHIP REGISTER DEFINITION Register 5 6 7 4 3 0.1 SEC 0 2 1 0.01 SEC 0 10 SEC 0 3 12/24 0 0 10 A/P HR 0 0 0 0SC RST 0 0 0 0 10 DATE 01-31 DATE 0 0 0 10 MONTH 01-12 MONTH 0 7 7 01-07 DAY 7 6 01-12 00-23 HOUR 7 5 00-59 MINUTES 10 MIN 7 0 00-59 0 7 4 00-99 SECONDS 7 2 Range (BCD) 0 7 1 0 10 YEAR YEAR 00-99 Figure 10–3. Timechip Register.
Real-Time Clock (DS 1215) AM/PM 12/24-Hour Mode The timekeeper is able to return data in a 12- or 24-hour mode, selected by bit 7 of register 3. When high, the 12-hour mode is selected; when low, the 24-hour mode is selected. In the 12-hour mode, bit 5 of register 3 becomes the AM/PM indicator; in the 24-hour mode, this bit becomes the second BCD bit, indicating tenths of hours. Oscillator and Reset Bits Reset and oscillator functions are controlled by bits 4 and 5 of register 4, the day register.
Chapter 11 COUNTER/TIMERS (8254) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 COUNTER/TIMER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Reset State . . . . . . . . .
Counter/Timers (8254) OVERVIEW Three programmable 16-bit counter/timers on the ZT 8809A are implemented in an Intel 8254 chip. These timers can handle inputs from DC to 8 MHz, and are useful for generation of accurate time delays under software control. This chapter describes the main components of the counter/timers, the method used to program them, and their use by STD DOS and the STD ROM Development System.
Counter/Timers (8254) BLOCK DIAGRAM Figure 11-1 illustrates the block diagram of the 8254. The data bus buffer is a three-state, bidirectional, 8-bit buffer that interfaces to the internal data bus on the ZT 8809A. The Read/Write Logic and the Control Word register generate control signals for the counter/timers, and address lines A0 and A1 control access to the three counter/timers and the Control Word register. As shown in the I/O map on page 5-16, the 8254 is addressed at 0040h through 0047h.
Counter/Timers (8254) COUNTER/TIMER ARCHITECTURE Each counter is fully independent and may operate in a unique mode. Only one counter/timer is described since the three counters are identical in operation. Figure 11-2 shows the internal block diagram of the counter/timer. Although the Control Word register is not a part of the counter/timer itself, its contents determine how the counter operates and it is therefore illustrated in the figure.
Counter/Timers (8254) The Status register shown in Figure 11-2, when latched, contains the current contents of the Control Word register and status of the output and null count flag. See the description of the Read-Back command on page 11-11. The OLM and OLL are two 8-bit latches. OL represents "Output Latch" and M and L refer to the high and low bytes of the count, respectively. These latches contain the count presently attained in the Counting Element (CE).
Counter/Timers (8254) OPERATION Reset State After power-up, the state of the 8254 is undefined. The mode, count value, and output of all counter/timers are undefined. How each counter operates is determined when it is programmed; each must be programmed before it can be used. Unused counters need not be programmed. The 8254 does not receive a reset signal; if a board reset occurs due to power-fail or a pushbutton reset, the timers continue to function as programmed.
Counter/Timers (8254) If a counter is programmed to read or write two-byte counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine that also writes into the same counter. If this happens, the counter will be loaded with an incorrect count.
Counter/Timers (8254) Read Operations It is possible to read the value of a counter without disturbing the count in progress. Three possible methods for reading the counters in the 8254 are a simple read operation, the Counter Latch command, and the Read-Back command. Simple Read The first method is to perform a simple read operation. We recommend that the counter CLK input first be inhibited by using the GATE input or by external logic if the clock input comes from the frontplane connector J3.
Counter/Timers (8254) I/O Address = 43h RD = 1 WR = 0 D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 0 0 X X X X SC1, SC0 - specify counter to be latched SC1 0 0 1 1 SC0 0 1 0 1 Counter 0 1 2 Read-Back Command D5, D4 - 00 designates Counter Latch Command X - don't care Note: Don't care bits (X) should be 0 to ensure future compatibility Figure 11–4. Counter Latch Command Format. The selected counter’s output latch (OL) latches the count at the time the Counter Latch command is received.
Counter/Timers (8254) If a counter is latched and then some time later latched again before the count is read, the second Counter Latch command is ignored. The count read will be the count at the time the first Counter Latch command was issued. Like the first method of reading the counter, the Counter Latch command requires that the count be read according to the programmed format. If the counter is programmed for two byte counts, two bytes must be read (though not necessarily one right after the other).
Counter/Timers (8254) Read-Back Command The third method of reading the 8254 is through use of the Read-Back command. This command allows you to check the count value, programmed mode, and current state of the OUT pin and Null Count flag of the selected counters. The Read-Back command is selected by writing to the Control Word register and has the format shown in Figure 11-3 on page 11-7.
Counter/Timers (8254) The counter status format is shown in Figure 11-5. Bits D5 through D0 contain the counter’s programmed mode exactly as written in the last Mode Control Word. OUTPUT via D7 contains the current state of the OUT pin. This allows you to monitor the counter’s output via software, possibly eliminating some hardware from a system.
Counter/Timers (8254) NULL COUNT bit D6 indicates when the last count written to the Count register (CR) has been loaded into the Counting Element (CE). The exact time this happens depends on the mode of the counter and is described in "Mode Definitions" on page 11-16, but until the count is loaded into the Counting Element (CE) it can’t be read from the counter. If the count is latched or read before this time, the count value will not reflect the new count just written.
Counter/Timers (8254) If multiple status latch operations of the counter(s) are performed without reading the status, all but the first are ignored; the status that is read is the status of the counter at the time the first status ReadBack command was issued. Both count and status of the selected counter(s) may be latched simultaneously by setting both COUNT* and STATUS* bits D5 and D4 equal to 0.
Counter/Timers (8254) Table 11-1 Read-Back Command Example.
Counter/Timers (8254) Mode Definitions The following modes are defined for use in describing the operation of the 8254. CLK Pulse: A rising edge, then a falling edge, in that order, of a counter’s CLK input. Trigger: A rising edge of a counter’s GATE input. Counter Loading: The transfer of a count from the CR to the CE (refer to Chapter 12, "Functional Description," page 12-7).
Counter/Timers (8254) If a new count is written to the counter, it will be loaded on the next CLK pulse and counting continues from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte disables counting. OUT is set low immediately (no clock pulse required). 2. Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the counting sequence to be synchronized by software.
Counter/Timers (8254) Mode 2: Rate Generator This mode functions like a divide-by-N counter. It is typically used to generate a real-time clock interrupt. OUT is initially high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the counter reloads the initial count, and the process is repeated. Mode 2 is periodic: the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles.
Counter/Timers (8254) Mode 3: Square Wave Mode Mode 3 is typically used for baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT is initially high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles.
Counter/Timers (8254) Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. One CLK pulse after the count expires, OUT goes low and the counter is reloaded with the initial count minus one. Succeeding CLK pulses decrement the count by two. When the count expires, OUT goes high again and the counter is reloaded with the initial count minus one. The above process is repeated indefinitely.
Counter/Timers (8254) This allows the sequence to be "retriggered" by software. OUT strobes low N + 1 CLK pulses after the new count of N is written. Mode 5: Hardware Triggered Strobe OUT is initially high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT goes low for one CLK pulse and then goes high again. After writing the Control Word and initial count, the counter is not loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count.
Counter/Timers (8254) Table 11-2 Gate Pin Operations Summary. Signal Status Modes Low or Going Low 0 Rising High Disables Counting —— Enables Counting 1 —— 1. Initiates Counting 2. Resets Output after Next Clock —— 2 1. Disables Counting 2. Sets Output Immediately High Initiates Counting Enables Counting Initiates Counting Enables Counting 3 1. Disables Counting 2.
Counter/Timers (8254) Operation Common to All Modes Programming When a Control Word is written to a counter, all Control Logic is immediately reset and OUT goes to a known initial state. No CLK pulses are required for this. Gate The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3, and 4, the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK. In Modes 1, 2, 3, and 5, the GATE input is rising-edge sensitive.
Counter/Timers (8254) Counter New counts are loaded and counters are decremented on the falling edge of CLK. The largest possible initial count is 0. This is equivalent to 216 for binary counting and 104 for BCD counting. The counter does not stop when it reaches zero. In Modes 0, 1, 4, and 5, the counter "wraps around" to the highest count (either FFFF hex for binary counting or 9999 for BCD counting) and continues counting. Modes 2 and 3 are periodic.
Counter/Timers (8254) Counter Use by STD DOS and STD ROM The use of these counters by STD DOS is limited to the use of counter/timer 0 as the DOS Timer 0 for its System Tick. This counter is programmed into Mode 2 as a rate generator for a periodic frequency of 18.2 ticks per second. The interrupt from this timer generates a request on level 0 (IR0) at the 8259A Interrupt Controller on board at this frequency. STD DOS maintains its software real-time clock with this System Tick.
Chapter 12 INTERRUPT CONTROLLER (8259A) Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 I/O PORT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 OPERATION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Rotating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specific Rotating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Mask Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Poll Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Triggering . . . . . . . . . . . . . . . . . . . .
Interrupt Controller (8259A) OVERVIEW The Programmable Interrupt Controller (PIC) is an Intel 8259A device (or equivalent). It is capable of monitoring eight interrupt inputs with programmable priority. When peripherals request service, the PIC interrupts the CPU with a pointer to a service routine for the highest priority device. This pointer is often called a "vector.
Interrupt Controller (8259A) OPERATION OVERVIEW The basic functions of the PIC are to resolve the priority of interrupt requests, issue a single interrupt request to the V20 based on that priority, and send the V20 a vector address pointing to the interrupt service routine for the proper device. When an interrupt request is enabled in the PIC and interrupts are enabled at the CPU, the occurrence of an interrupt prompts the CPU to enter its interrupt acknowledge cycle.
Interrupt Controller (8259A) All 256 interrupt types are located in absolute memory locations 0 through 3FFh, which make up the V20’s interrupt vector table (see Figure 12-1). Each type in the interrupt vector table requires 4 bytes of memory and stores a code segment address and an instruction pointer address. Locations 0 through 3FFh should be reserved for the interrupt vector table alone.
Interrupt Controller (8259A) When the V20 receives an interrupt vector byte from the 8259A, it multiplies its value by four to acquire the address of the interrupt type. For example, if the interrupt vector byte specifies a type of 128 (80h), the vectored address in V20 memory is 4 x 80h, which equals 200h. Program execution is then vectored to the service routine whose address is specified by the code segment and the instruction pointer values within type 128 located at 200h.
Interrupt Controller (8259A) FUNCTIONAL DESCRIPTION Figure 12-2 shows a block diagram of the 8259A. The PIC is divided into eight major blocks for explanation purposes. Each of these functional blocks is described in the following sections.
Interrupt Controller (8259A) Interrupt Request Register (IRR) All interrupt requests are input to the Interrupt Request register (IRR). The 8-bit IRR maintains a bit position for each interrupt input. A requesting interrupt sets the bit position to logical 1. The bit is automatically reset during the interrupt acknowledge cycle. The application program can read the IRR to determine the status of the requesting interrupts. The PIC has eight interrupt inputs, IR0 through IR7.
Interrupt Controller (8259A) Priority Resolver (PR) All interrupt requests are latched into the IRR. Those not masked by the IMR are input to the Priority Resolver (PR) to determine which is to be serviced. The interrupt request with the highest priority is transferred from the IRR to the ISR during the interrupt acknowledge cycle. The PIC includes several programmable operating modes that define the rules by which the PR determines the highest priority interrupt request.
Interrupt Controller (8259A) Read/Write Control Logic The Read/Write Control Logic controls command and data transfer between the PIC and the CPU. This functional block selects a PIC register and determines the direction of data travel based on the address and I/O control inputs. Initialization and Operation Registers Several registers in the PIC store programmed information regarding the handling of interrupts.
Interrupt Controller (8259A) PROGRAMMABLE REGISTERS The PIC is initialized with the Initialization Control Words 1 through 4 (ICW1-4). This must take place before enabling CPU interrupts, since the 8259A does not receive a power-up reset pulse and is in an undetermined state until initialized. Operation of the PIC is then controlled with Operation Control Words 1 through 3 (OCW1-3), which handle operation and read or write access to various registers within the PIC.
Interrupt Controller (8259A) Initialization Control Words (ICW1-4) Initialization of the PIC consists of writing from three to four bytes, or Initialization Control Words (ICWs), to the PIC in the proper order. The format of these ICWs is shown on page 12-13. The sequence in which these words are programmed is in order of their names, ICW1 through ICW4. ICW1, ICW2, and ICW4 are always required; ICW3 is not always programmed, depending upon the information supplied in ICW1 and ICW2.
Interrupt Controller (8259A) ICW1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 LTIM 0 S 1 I/O ADDRESS = 20h 1 - SINGLE 0 - NOT SINGLE 1 - LEVEL TRIGGERED INPUT 0 - EDGE TRIGGERED INPUT ICW2 D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 0 0 0 I/O ADDRESS = 21h SET BY 8259A ACCORDING TO INTERRUPT LEVEL MOST SIGNIFICANT BITS OF VECTORING BYTE ICW3 (Master Device) D7 D6 D5 D4 D3 D2 D1 D0 S7 S6 S5 S4 S3 S2 S1 S0 I/O ADDRESS = 21h 1 - IR INPUT HAS A SLAVE 0 - IR INPUT DOES NO
Interrupt Controller (8259A) ICW2 The second Initialization Control Word (ICW2), also required in all modes of operation, is located at I/O address 21h. It consists of the following: a) For programming as a master PIC with slaves on all inputs, write 00h in ICW2. Although in this case ICW2 conveys no information, it is required to prepare the master PIC for either ICW3 or ICW4 (or both) to follow.
Interrupt Controller (8259A) ICW4 The fourth Initialization Control Word (ICW4), required for all modes of operation, is located at I/O address 21h. It consists of the following: a) Bits 0 and 3 are both logical 1s to identify the word as ICW4 for an 8088 CPU and to denote that the hardware is configured for buffered operation. These bits must both be set to 1 for proper operation of the PIC on the ZT 8809A. b) Bit 1 programs the End-Of-Interrupt (EOI) function.
Interrupt Controller (8259A) ICW Summary In summary, three or four ICWs are required to initialize the master and each slave PIC. Specifically: • Master PIC - No Slaves: ICW1, ICW2, ICW4 • Master PIC - With Slave(s): ICW1, ICW2, ICW3, ICW4 • Each Slave PIC: ICW1, ICW2, ICW3, ICW4 To initialize the PICs (master and slave), proceed as follows: 1. Disable system interrupts by executing a CLI (Clear Interrupt Flag) instruction. 2.
Interrupt Controller (8259A) OCW1 D7 D6 D5 D4 D3 D2 D1 D0 M7 M6 M5 M4 M3 M2 M1 M0 I/O ADDRESS = 21h INTERRUPT MASK 1 = MASK SET 0 = MASK RESET OCW2 D7 D6 D5 D4 D3 D2 D1 D0 R SL EOI 0 0 L2 L1 L0 I/O ADDRESS = 20h BCD LEVEL TO BE RESET OR PUT INTO LOWEST PRIORITY 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 0 0 Non-specific EOI Specific EOI Rotate on Non-Specific EOI Command Rotate in Automatic EOI Mode (Set)
Interrupt Controller (8259A) OCW1 OCW1 is used solely for 8259A masking operations. It is located at I/O address 21h. It provides a direct link to the IMR (Interrupt Mask register). The processor can write to or read from the IMR via OCW1. The OCW1 bit definition is as follows: M0-M7 The M0-M7 bits are used to control the masking of interrupt request (IR) inputs. If an M bit is set to 1, it masks the corresponding IR input. A logical 0 clears the mask, thus enabling the IR input.
Interrupt Controller (8259A) EOI The EOI bit is used for all End-Of-Interrupt commands (not an automatic End-Of-Interrupt mode). If EOI is set to 1, a form of End-Of-Interrupt command is executed depending on the state of the SL and R bits. If EOI is 0, an End-Of-Interrupt command is not executed. SL The SL bit is used to select a specific level for a given operation. If SL is set to 1, the L0-L2 bits are enabled. The operation selected by the EOI and R bits is executed on the specified interrupt level.
Interrupt Controller (8259A) RR The RR bit is used to execute the read register command. If RR is set to 1, the read register command is issued and the state of RIS determines the register to be read. If RR is 0, the read register command is not issued. P The P bit is used to issue the poll command. If P is set to 1, the poll command is issued. If it is 0, the poll command is not issued. The poll command overrides a read register command if they are set simultaneously.
Interrupt Controller (8259A) 8259A I/O PORT ADDRESSES The 8259A programmable interrupt controller on the ZT 8809A uses I/O port addresses 20h or 21h. I/O address 20h is used to write ICW1, OCW2, and OCW3 and to read IRR, ISR, and the interrupt level (IL) (when the PIC is programmed for poll mode). I/O address 21h is used to write ICW2-ICW4 and to read IMR. Slave PICs, if employed, are accessed via the STD bus, and their I/O addresses are determined by the board manufacturer.
Interrupt Controller (8259A) INTERRUPT ASSIGNMENTS ON THE ZT 8809A The PIC has eight interrupt inputs, IR0 through IR7. Figure 12-5 illustrates the interrupt options available on the ZT 8809A. Each interrupt source is available at a wirewrap pin, and one of each pair of wirewrap pins is jumper selected to drive the interrupt at the PIC. In the figure, interrupt sources preceded by bullets are interrupts required by STD DOS; do not change these if you use STD DOS on the ZT 8809A.
Interrupt Controller (8259A) Jumper Selections 8087 Interrupt A Timer 0 B INTRQ1* A FP1* B INTRQ* A Timer 2 B FP3* A COM2* B Timer 1 A COM1* B Power Fail* FP5* A FP6* A INTRQ2* B LPT1 FP7* A B B Interrupt Level W5 IRO W4 IR1 W6 IR2 W7 IR3 W8 IR4 W2, W9 IR5 W3, W10 IR6 W11 IR7 Figure 12–5. 8259A Interrupts.
Interrupt Controller (8259A) OPERATION OF THE INTERRUPT CONTROLLER Interrupt operation of the 8259A falls under three categories: priorities, triggering, and status. Each category uses various modes and commands, as discussed below. Additional information can be found in Intel’s 8259A data sheet and application note AP-59.
Interrupt Controller (8259A) Special Fully Nested Mode This mode is used only when one or more PICs are cascaded to the ZT 8809A master PIC. In the cascade mode, if a slave receives a higher priority interrupt request than one that is in service, it will not be recognized by the master. This is because the master’s ISR bit is set to ignore all requests of equal or lower priority.
Interrupt Controller (8259A) Automatic Rotating Mode In this mode, the interrupt priority rotates. Once an interrupt on a given input is serviced, that interrupt assumes the lowest priority. Thus, if a number of simultaneous interrupts occur, the priority rotates among the interrupts in numerical order. For example, if interrupts IR4 and IR6 request service simultaneously, IR4 receives the highest priority.
Interrupt Controller (8259A) The special mask mode is useful when one or more interrupts are masked. If for any reason an input is masked while it is being serviced, the lower priority interrupts are disabled. However, it is possible to enable the lower priority interrupt with the special mask mode. In this mode, the lower priority lines are enabled until the special mask mode is reset. Higher priorities are not affected.
Interrupt Controller (8259A) Level-Triggered Mode When in the level-triggered mode, the 8259A recognizes any active (high) level on an IR input as an interrupt request. If the IR input remains active after an EOI command has been issued (resetting its ISR bit), another interrupt is generated. This occurs if the processor INT pin is enabled. Unless repetitious interrupt generation is desired, the IR input must be brought to an inactive state before an EOI command is issued in its service routine.
Interrupt Controller (8259A) Edge-Triggered Mode In the edge-triggered mode, the 8259A recognizes only interrupts that are generated by an inactive (low) to active (high) transition on an IR input. The edge-triggered mode incorporates an edge-lockout method of operation. After the rising edge of an interrupt request and acknowledgment of the request, the positive level of the IR input does not generate further interrupts on this level.
Interrupt Controller (8259A) A brief review of the registers’ general descriptions follows. • IRR (Interrupt Request Register): Specifies all interrupts requesting service. • ISR (In-Service Register): Specifies all interrupt levels being serviced. • IMR (Interrupt Mask Register): Specifies all interrupt levels that are masked. To read the contents of the IRR or ISR, you must first issue the appropriate read register command (read IRR or read ISR) to the 8259A.
Interrupt Controller (8259A) EOI COMMANDS Upon completion of an interrupt service routine, the 8259A needs to be notified so its ISR can be updated. This is done to keep track of interrupt levels being serviced and their relative priorities. Three different End-Of-Interrupt (EOI) formats are available. These are the nonspecific EOI command, the specific EOI command, and the automatic EOI mode. Which EOI you select depends upon the interrupt operations you wish to perform.
Interrupt Controller (8259A) Specific EOI Commands A specific EOI command sent from the microprocessor lets the 8259A know when a service routine of a particular interrupt level is completed. Unlike a nonspecific EOI command, which automatically resets the highest priority ISR bit, a specific EOI command specifies an exact ISR bit to be reset. One of the eight IR levels of the 8259A can be specified in the command.
Interrupt Controller (8259A) Special consideration should be given, however, when deciding to use the automatic EOI mode because it disturbs the fully-nested mode. In the automatic EOI mode the ISR bit of a routine in service is reset immediately after it is acknowledged, thus leaving no designation in the ISR that a service routine is being executed. If any interrupt request occurs during this time (and if interrupts are enabled), it will be serviced regardless of its priority, low or high.
Interrupt Controller (8259A) RESET The 8259A does not receive a reset signal upon power-up or when pushbutton reset is applied to the ZT 8809A. The part powers up in an undefined state and may drive the interrupt request to the processor. You MUST initialize the 8259A prior to enabling processor interrupts via software.
Chapter 13 ZT 88CT08A/88CT09A CMOS BOARDS Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DIFFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Family (CT vs. C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of 80C88 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addition of Optional 8087(-2) . . . . . . . . . . . . . .
ZT 88CT08A/88CT09A CMOS Boards FUNCTIONAL DIFFERENCES Logic Family (CT vs. C) There are two main logic families to choose from when using fast CMOS logic: CMOS with TTL-compatible inputs and CMOS with CMOS-compatible inputs. If your system uses CMOS logic with other CMOS logic, the inputs need only be CMOS-compatible. Such parts are designated by a "C" in the device name; for example, 74AC573.
ZT 88CT08A/88CT09A CMOS Boards Use of 80C88 Processor The ZT 88CT09A uses an 80C88 microprocessor instead of the V20 used on non-CMOS versions. The 80C88 allows for a slower clock speed, even a halted clock, for extremely low power operation. Although the V20 is CMOS and also has a low power standby mode, it does not allow for a clock speed slower than 2 MHz. The slowdown and stopped clock modes are available on the ZT 88CT09A and are described beginning on page 13-4.
ZT 88CT08A/88CT09A CMOS Boards Addition of Optional 8087(-2) As described in Chapter 7, "Numeric Data Processor," a special module is available from Ziatech to allow addition of the 8087 Numeric Data Processor to the ZT 8808A and ZT 8809A. This module, known as the zSBC 337, normally comes with the commercial 8087 or 8087-2 part mounted on the board. The "-2" part is a faster part required for use with the ZT 8809A.
ZT 88CT08A/88CT09A CMOS Boards Slowing down the processor clock is useful for power-critical applications that don’t always require full speed processing. For example, a situation may exist in which processing occurs only during certain time intervals. The software can slow down the clock for noncritical processing times, yet continue to process in order to monitor non-critical events such as checking time of day.
ZT 88CT08A/88CT09A CMOS Boards If the processor must operate at slow processor speed 100% of the time, hardware jumper W46A may select this, leaving the SLIN* bit free for printer use. The board is shipped from the factory with both W46A and W46B removed, selecting full processor speed and leaving SLIN* free for printer use. You may not use this feature with STD DOS, which is a timedependent application.
ZT 88CT08A/88CT09A CMOS Boards The mechanism used to stop and restart the processor clock is part of the 82C85 clock chip, which is supplied only on the ZT 88CT08A and ZT 88CT09A boards. This chip monitors the status lines from the CPU. When a processor halt status is seen on those status lines, the 82C85 halts its clock output. This in turn stops the processor. When an interrupt is seen out of the 82C59A Programmable Interrupt Controller on board, the 82C85 then restarts the clock.
ZT 88CT08A/88CT09A CMOS Boards ELECTRICAL/ENVIRONMENTAL DIFFERENCES Increased Temperature Range The ZT 8808A and ZT 8809A boards are rated for operation in ambient temperatures of 0 to +65˚ C in <95% humidity (noncondensing). The CMOS parts on the ZT 88CT08A and ZT 88CT09A increase this range to -40 to +85˚ C in <95% humidity (non-condensing). Reduced Power Consumption The CMOS logic used on the ZT 88CT08A and ZT 88CT09A greatly reduces power consumption.
ZT 88CT08A/88CT09A CMOS Boards If you take advantage of the Clock Slowdown feature, typical power consumption is reduced to 132 mA with one 64 Kbyte EPROM and one 128 Kbyte RAM and a 100 pF load on the STD bus. This shows a power reduction of approximately 30 percent. To further reduce power, use the halt with interrupt restart method (see page 3-29). During the time the processor is halted, power consumption measures 115 mA with the same memory configuration and capacitive load.
Appendix A JUMPER CONFIGURATIONS Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 JUMPER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 OVERVIEW This appendix contains detailed descriptions of the ZT 8809A jumper selectable options. The jumper descriptions outline the use of the ZT 8809A jumpers in numerical order.
J5 J4 Jumper Configurations W1 W2 W4 W5 W6 W7 W8 W9 W10 W11 W3 A B A B A B A B A B A B A B A B W12 Figure A–1. W1 - W12 Jumper Block.
Jumper Configurations JUMPER DESCRIPTIONS Table A-1 Jumper Descriptions. JUMPER # DESCRIPTION W1 Install this jumper when using the AC Power-Fail Detect option. This option requires use of the ZT 90071 24 VAC Transformer plugged into connector J5. The ZT 8809A power-fail circuitry is then able to detect AC power failure and generate a nonmaskable interrupt to the processor for early warning of impending DC power failure. Factory default removes this jumper.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W2 Jumper W2 ties the power-fail non-maskable interrupt request (PNMI*) or the frontplane interrupt request 5 (FP5*) to the interrupt request 5 (IR5) on the interrupt controller, depending upon the state of jumper W9. Factory default installs this jumper.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W4(A,B) Installing W4A ties the STD bus pin INTRQ1* (previously RESERVED) to the interrupt request 1 (IR1) on the interrupt controller, as opposed to installing W4B, which ties the frontplane interrupt request 1 (FP1*) to IR1. Factory default installs W4A for STD DOS and STD ROM systems.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W6(A,B) Jumper W6A brings the STD bus interrupt request (INTRQ*), inverted once, to the interrupt request 2 (IR2) on the interrupt controller. Jumper W6B brings the output of timer 2 to IR2. Factory default installs W6A.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W8(A,B) Install W8A to bring timer 1 output to the interrupt request 4 (IR4) on the interrupt controller. Install W8B to bring serial port 1 (COM1) interrupt request to IR4. Factory default installs W8B.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W10(A,B) Select jumper W10A to bring the frontplane interrupt request 6 (FP6*) to interrupt request 6 (IR6) on the interrupt controller, provided jumper W3 is also installed. Select jumper W10B to bring the STD bus INTRQ2* pin 50 to IR6, assuming again jumper W3 is installed. (Refer to the descriptions of jumpers W3 and W62.) Factory default installs W10B for STD DOS and STD ROM.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W11(A,B) Install jumper W11A to bring frontplane interrupt request 7 (FP7*) to interrupt request 7 (IR7) on the 8259A interrupt controller. Install jumper W11B to bring the printer interrupt request (LPT1) to IR7. Factory default installs W11A.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W12 Install jumper W12 to bring battery ground reference to the timekeeper and 32 Kbyte RAM, and any other RAM chosen for battery backup by jumpers W35 and W38. Remove this jumper to erase the RAM (the RAM drive for DOS systems) and timekeeper. For rapid erasure of RAM and timekeeper while W12 is removed, temporarily short the W12 pin nearest the extractor to STD bus ground pins 3 and 4. Factory default installs W12.
Jumper Configurations J6 A W13 B J3 TIMER LPT COUNTER W14 A W15 B W16 A B W17 A B W18 J2 COM2 W19 W20 A W29 B W21 W22 W30 W31 W23 W32 W24 J1 COM1 W25 W26 W27 W28 ZT 8809A REV. A Figure A–2. W13 - W32 Jumper Block.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W13(A,B) Jumpers W13 A and B control the enabling and disabling of the RS-422/485 drivers available on serial channel 2. Install W13A to disable the drivers unconditionally. Remove both W13A and W13B to enable the drivers unconditionally, as for an RS-422 interface.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W13(cont.) Refer to the descriptions of jumpers W16-18 and W21 if attempting to use the RS-422/485 drivers to avoid interference by the RS-232C drivers and receivers. Factory default installs jumper W13A. Refer to Chapter 9 for further details on the printer interface and Chapter 8 for further details on the serial ports.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W14 Jumper W14 controls enabling and disabling of RS-422/485 receivers available on serial channel 2. Install W14 to disable the receivers and remove it to enable the receivers. Refer to the table on page A-17 if attempting to use the RS-422/485 receivers to avoid interference by RS-232-C drivers and receivers. Factory default installs W14.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W15(A,B) Install W15A to bring connector J2 pin 13 to the input of the RS-422/485 receiver at serial data in (SIN1) on serial port 2. Install W15B to ground pin 13 of J2 for use of the RS-232-C drivers and receivers on serial port 2. Factory default installs W15B. Refer to page A-17 for complete serial jumper assignments.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W17(A,B) Install W17A to bring J2 pin 1 to the RS-422/485 driver from serial port 2 serial data out (SOUT1). Install W17B to ground J2 pin 1 to provide shell ground to the RS-232-C interface. Remove both W17A and W17B to leave J2 pin 1 open. Factory default installs W17B.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W14-W19, The following table shows jumper assignments for use of serial port 2 (COM2) as either an RS-232-C port in DCE or DTE mode or as an RS-422/485 port. Factory default is DCE mode, with the RS-422/485 drivers and receivers disabled. W21-W22, W29-W32 Be sure to read the description of W13 if using the RS-422/485 drivers and the description of W66 to enable COM2.
Jumper Configurations J6 W13 J3 TIMER COUNTER LPT W14 W15 W16 J2 COM2 W17 W18 W19 W20 W21 W29 W22 W30 W31 W23 W32 W24 W25 J1 COM1 W26 W27 W28 ZT 8809A REV. A Figure A–3. COM2 Configured as RS-232-C DCE.
Jumper Configurations J6 W13 J3 TIMER LPT COUNTER W14 W15 W16 J2 COM2 W17 A B W18 W19 W20 A W29 B W21 W22 W30 W31 W23 W32 W24 W25 J1 COM1 W26 W27 W28 ZT 8809A REV. A Figure A–4. COM2 Configured as RS-232-C DTE.
Jumper Configurations J6 A W13 B J3 TIMER COUNTER LPT W14 W15 B W16 B W17 B W18 J2 COM2 W19 W20 B W29 W21 W22 W30 W31 W23 W32 W24 J1 COM1 W25 W26 W27 W28 ZT 8809A REV. A Figure A–5. COM2 Configured as RS-422 DCE.
Jumper Configurations J6 A W13 B LPT J3 TIMER COUNTER W14 W15 B W16 B W17 B W18 J2 COM2 W19 W20 B W29 W21 W22 W30 W31 W23 W32 W24 W25 J1 COM1 W26 W27 W28 ZT 8809A REV. A Note: Select W13B and refer to Chapter 9 if controlling the RS-485 driver output enables dynamically (in software via printer port signal INIT). Figure A–6. COM2 Configured for RS-485 Operation.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W23-W28 (DCE †,DTE) These jumpers allow reconfiguration of the RS-232-C serial port 1 at J1 for DCE or DTE. Install W23 through W28 to configure the port as DCE. To configure the port for DTE, the three jumper pairs W23-24, W25-26, and W27-28 must be crossed over as shown in Figure A-7. Factory default ships serial port 1 as DCE in order to allow communication with COM1 on the IBM PC (see Figure A-8).
Jumper Configurations J6 A W13 B J3 TIMER COUNTER LPT W14 W15 B W16 B W17 B W18 J2 COM2 W19 W20 B W29 W21 W22 W30 W31 W23 W32 W24 J1 COM1 W25 W26 W27 W28 ZT 8809A REV. A Figure A–7. COM1 Configured for DTE Operation.
Jumper Configurations J6 A W13 B J3 TIMER COUNTER LPT W14 W15 B W16 B W17 B W18 J2 COM2 W19 W20 B W29 W21 W22 W30 W31 W23 W32 W24 J1 COM1 W25 W26 W27 W28 ZT 8809A REV. A Figure A–8. COM1 Configured for DCE Operation. (Default jumper configuration.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W34 Install W34 to bring the 1.19318 MHz clock to the timer 2 clock input and to J3 pin 8. Remove W34 to disconnect this clock. This requires an external source on J3 pin 8 to clock the timer and is necessary to prevent an open circuit on the clock input. Factory default installs this jumper. W34 Function IN † OUT Timer 2 clock input is 1.
Jumper Configurations W34 W33 W35 A B A W45 W44 W40 W38 B W36 A B B W42 W41 A A B B A W43 W39 A B W46 A B W68 Figure A–9. W33-W36, W38-W46, W68 Jumper Blocks.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W36(A,B) Select W36B to insert one wait state on all CPU cycles. Select W36A to omit any wait states generated by the ZT 8809A. This still allows for off-board wait requests. Factory default installs W36A.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W38(A,B) Install jumper W38A to battery back the RAM 3/EPROM 0 socket at 3D1. This is possible only when a CMOS static RAM is installed in the socket. Install jumper W38B to tie pin 16 of that socket directly to ground. Factory default installs W38B. Note: Since the RAM in 3D1 is a possible location for a RAM drive in a 640 Kbyte system, jumper W38A allows independent battery backup of a RAM drive.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W39 This jumper controls the use of the printer port signal ERROR*. Removing W39 allows for the use of ERROR* by the printer. Installing W39 allows the STD bus interrupt request signal (INTRQ*), inverted once, to be read as a status bit at the printer port signal ERROR*. This assumes that ERROR* is not being used at the printer.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # W40-W42, W43 (A,B) Assign these jumpers to configure socket 3D1 for the proper chip type installed. Refer to Figure A-10 on page A-31. The memory address space allocated for this socket is assigned according to jumper assignments W55-W59. Factory default assigns a 128 Kbyte EPROM for an STD DOS EPROM drive to socket 3D1. For STD ROM systems, factory default assigns a 64 Kbyte EPROM to socket 3D1.
Jumper Configurations JUMPER PIN ASSIGNMENTS 16K byte EPROM W40 W45AW44A W41 A B W39 W41 W45BW44B W42 W39 B A W43 32K byte EPROM 64K BYTE EPROM or 128K byte EPROM W44A-W40 W41-W42 W41-W42 W43B 256 byte EPROM W40 W42-W43A 128K byte RAM or 32K byte RAM W44A-W40 W41 W41-W42 W43B W42-W43A W42 W43 NOTE: Dotted lines represent wire wraps. Only jumpers W40-W43 and W44 affect socket 3D1. Shaded areas should remain jumpered as appropriate for your application. Figure A–10. Socket 3D1 Configuration.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W44-45(A,B), These three jumpers select the chip size to be used in the EPROM socket 5D1. The memory address space occupied by the EPROM is determined by the jumper assignments W57-W59, which must also be selected for proper operation. Socket 3D1 occupies the lower half (if containing EPROM) and socket 5D1 occupies the upper half of the on-board EPROM address space.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W46(A,B) Installing W46B allows the printer port signal Select In* (SLIN*) to control the speed of operation of the processor via the Slow/Fast (SLO/F) input to the 82C85 on ZT 88CT08A and ZT 88CT09A boards only. ZT 8808A and ZT 8809A boards contain 82C84A parts that do not receive this signal, and altering the SLIN* bit on these boards does nothing.
Jumper Configurations C J7 W50 A B W66 W37 W47 A A B B W49 W48 Figure A–11. W37, W47-50, W66-W67 Jumper Blocks.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W47(A,B), These jumpers control the interrupt scheme. Install jumper W47B to use the on-board 8259A as a single or master interrupt controller, allowing the ZT 8809A to drive the cascade address lines (CAS0-2) over STD bus address lines A8-A10, respectively.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W50(A,B) Install jumper W50A to bring the interrupt output (INT) from the on-board 8259A to the CPU interrupt input (INT). Install W50B to bring the STD bus interrupt request (INTRQ*), inverted once, directly to the CPU INT input. This disconnects the onboard 8259A INT. Do this when using an off-board master 8259A with or without slaves. Factory default installs W50A.
W48 B W49 B A J7 W50 W66 A B A W47 Jumper Configurations W51 W52 W53 W54 W55 W56 W57 W58 W59 Figure A–12. W51 - W59 Jumper Block.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W51,W52 Install W51 and remove W52 to bring the 8087 interrupt output (NDPINT) from connector J7 to a PAL implemented "OR" gate that drives the CPU non-maskable interrupt input (NMI). Two other sources for NMI are power-fail and STD bus nonmaskable interrupt request (NMIRQ*). Note that power-fail causes an NMI only if jumper W1 is installed.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W53 Install W53 to enable the ZT 8809A to drive the STD bus signal DCPWRDWN*, pin 6, when DC power is failing. The ZT 8809A can detect DC power failure and AC power failure with the optional AC transformer. The DCPWRDWN* is sent to allow other boards in the system to protect their static RAM at the same time as the processor. Removing W53 prevents the ZT 8809A from driving the DCPWRDWN* signal.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W54 Remove W54 when installing the optional zSBC 337 module for use of an 8087 Numeric Data Processor with the ZT 8809A. Install W54 when this module is not to be used. Factory default installs W54.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W55-W59 These jumpers control the memory map for sockets 3D1, 5D1, 7D1, and 9D1. They also affect the location of the 32K battery-backed RAM (BRAM). The "Memory Addressing" table on the following three pages clearly describes the memory map for each jumper combination. An "X" indicates that the jumper may be in or out. Factory defaults for STD DOS and STD ROM are shown below.
A-42 In In In In In In In In In In In In In In Out In Out Out Out Out Disabled Disabled 40000-5FFFF E0000-FFFFF Out 80000-9FFFF E0000-FFFFF 0-1FFFF 0-1FFFF 0-1FFFF In Out In 80000-BFFFF C0000-FFFFF 0-1FFFF 0-1FFFF In E0000-EFFFF F0000-FFFFF 0-1FFFF Out In Out F0000-F7FFF F8000-FFFFF 0-1FFFF 7D1 Out Out C0000-DFFFF E0000-FFFFF 0-1FFFF Out In D/A 5D1 D8000-DFFFF Disabled 20000-3FFFF D8000-DFFFF 78000-7FFFF B8000-BFFFF D8000-DFFFF E8000-EFFFF F0000-F7FFF 32 K BRAM 20000-3FF
W55 W56 W57 W58 W59 In Out In In In W67 In & SLIN Low >> In Out In In Out W67 In & SLIN Low >> In Out In Out In W67 In & SLIN Low >> In Out In Out Out W67 In & SLIN Low >> In Out Out In In W67 In & SLIN Low >> In Out Out In Out W67 In & SLIN Low >> In Out Out Out In W67 In & SLIN Low >> In Out Out Out Out W67 In & SLIN Low >> 3D1 Disabled 80000-9FFFF F0000-F7FFF 80000-9FFFF E0000-EFFFF 80000-9FFFF C0000-DFFFF 80000-9FFFF 80000-BFFFF " 80000-9FFFF " 40000-5FFFF 4-5F & 8-9F Disabled 80000-9FFFF 5D1 Disabled
A-44 Out Out Out Out Out Out Out Out Out In E0000-FFFFF Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Out 80000-9FFFF E0000-FFFFF Disabled In B8000-BFFFF Disabled Disabled D8000-DFFFF D8000-DFFFF 78000-7FFFF D8000-DFFFF Disabled Disabled Disabled E8000-EFFFF F0000-F7FFF Reserved 32 K BRAM Disabled Disabled 80000-BFFFF C0000-FFFFF Disabled E0000-EFFFF F0000-FFFFF Out In In Out Out Disabled In Out Out Disabled Reserved Resv'd Out F0000-F7F
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W60 Install W60 to ground the STD bus signal MEMEX. Remove W60 to pull MEMEX up through a 2.2 kΩ resistor to +5 V. Factory default installs W60. W60 Function IN † OUT MEMEX tied to Logic Ground MEMEX tied to Vcc W61 Install W61 to ground the STD bus signal IOEXP. Remove W61 to pull IOEXP up through a 2.2 kΩ resistor to +5 V. Factory default installs W61.
Jumper Configurations W61 W60 W62 W63 W64 A B A B W65 Figure A–13. W60 - W65 Jumper Block.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W62 Install W62 to allow the STD bus signal CNTRL* to be driven by the ZT 8809A clock signal. Remove W62 to prevent the ZT 8809A from driving CNTRL*. The CNTRL* signal can be driven by an external source in the STD backplane to the interrupt controller IR6 via an inverter, which requires the removal of W62. This allows for an extra interrupt request through the STD bus backplane.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W63 Install W63 to connect the STD bus auxiliary ground (AUXGND) signal to the STD bus logic ground (GND). These two grounds must be attached for proper operation of the RS-232-C drivers and receivers. Ziatechsupplied card cage and power supply assemblies already connect AUXGND with GND in the backplane; therefore, installation of W63 is not necessary. Remove W63 to disconnect AUXGND from GND on the ZT 8809A.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W64(A,B) Install W64A to drive the STD bus write signal (WR*) during memory cycles with the 8288 Memory Write control (MWTC*). Install W64B to drive WR* with the 8288 Advanced Memory Write control (AMWC*). The AMWC* signal starts one clock earlier with respect to MWTC* in the four clock CPU cycle. Factory default installs W64B.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W65(A,B) Install W65B to drive the STD bus write signal (WR*) during I/O cycles with the 8288 I/O Write control (IOWC*). Install W65A to drive WR* with the 8288 Advanced I/O Write control (AIOWC*). The AIOWC* signal starts one clock earlier with respect to IOWC* in the four clock CPU cycle. Factory default installs W65A.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W66 Removing jumper W66 allows an off-board serial port to be mapped into the system at the COM2 I/O port address. This is useful, for example, when a separate serial card such as the ZT 8841 is to be used for COM2. Factory default installs W66. The location of W66 is shown in Figure A-11 on page A-34.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W67 Installing jumper W67 connects the parallel port signal SLIN* to the memory decoder. This allows 256K EPROMs to be used in socket 5D1 in conjunction with 640K of system RAM. Writing a "1" to bit 3 of the Line Printer Control Register allows access to the lower 128K of a 256K EPROM placed in socket 5D1. Jumpers W55 and W56 must also be selected correctly for a 256K device.
Jumper Configurations Table A-1 Jumper Descriptions (continued). JUMPER # DESCRIPTION W68(A,B) Memory size selection jumper for socket 7D1. The "B" position connects Vcc to socket 7D1 pin 30 for 128K and smaller RAM devices. The "A" position connects address line "LA17" to socket 7D1 pin 30 for 512K RAM devices. Factory default installs W68B. The location of W68 is shown in Figure A-9 on page A-26.
Jumper Configurations TIMER COUNTER W12 W23 W24 W25 W26 W27 W28 W16 W17 W18 W19 W20 W21 W22 COM1 W29 W30 W31 W32 A W4 W5 W6 W7 W8 W9 W10 W11 W1 W14 W3 A W15 B W2 A B W13 COM2 LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 W47 B A W49 A B W68 W48 W37 A B W46 A B B A W66 B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A B W50 A W60 W62 W61 Figure A–14. ZT 8809A User Configuration. A-54 W63 ZT8809A REV.
Jumper Configurations TIMER COUNTER W17 W18 W19 W20 W21 W22 W16 COM1 W12 W29 W30 W31 W32 ZT8809A REV. A A W4 W5 W6 W7 W8 W9 W10 W11 W1 W14 W3 A W15 B W2 A B W13 COM2 W23 W24 W25 W26 W27 W28 INTERRUPTS LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 B A 32K SRAM W49 W68 A B STD ROM W47 B A W48 A B W37 A B W46 W66 B W64 W65 W51 W52 W53 W54 W55 W56 W57 W58 W59 A A B W50 W60 W62 W63 W61 Figure A–15. Non-DOS Factory Default Jumper Configuration.
Jumper Configurations TIMER COUNTER LPT A B W36 A B W33 W35 W34 A B B A W38 W39 W67 W40 W43 W44 W45 W66 W68 128K RAM 128K RAM B A 256K EPROM W49 128K EPROM W47 B A A B W48 W37 A B W46 A B B A B W51 W52 W53 W54 W55 W56 W57 W58 W59 A W64 W65 W50 W60 W62 W63 W61 Figure A–16. ZT 8809A Configured for STD DOS. A-56 ZT8809A REV.
Appendix B SPECIFICATIONS Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 ELECTRICAL AND ENVIRONMENTAL . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Battery Backup Characteristics . . . . . . . . . . . . . . . . . . .
Specifications ELECTRICAL AND ENVIRONMENTAL The ZT 8809A meets the electrical and environmental parameters of the STD-80 Series Bus Specification. These parameters are outlined below. Absolute Maximum Ratings ZT 8808A/8809A Supply Voltage, Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 7 V Supply Voltage, AUX +V . . . . . . . . . . . . . . . . . . . . . . . . 0 to 13 V Supply Voltage, AUX -V . . . . . . . . . . . . . . . . . . . . . . . . 0 to -13 V Operating Temperature . . . . .
Specifications Battery Backup Characteristics (Vcc < 4.75 V) 32 Kbyte Static RAM Data Retention and Real-Time Clock Operation: 1.5 years min., 10 years typ. Adding 128 Kbyte Static RAM: 1.0 years min., 10 years typ. STD Bus Loading Characteristics The unit load is a convenient method for specifying the input and output drive capability of STD bus cards.
Specifications Table B-1 STD Bus Signal Loading, P Connector.
Specifications Table B-2 STD Bus Signal Loading, E Connector.
Specifications MECHANICAL The ZT 8809A meets the STD-80 Series Bus Specification for all mechanical parameters except component lead length protruding from the back of the board. Non-compliance with this parameter is due to the battery socket pins. The specification requires no more than 0.04 inches; the battery socket pins protrude 0.125 inches. Care should be taken when mounting a board next to the ZT 8809A in the card cage, so as to not short the battery socket pins to an adjacent card.
Specifications Table B-3 Mechanical Specifications. Board Length . . . . . . . . . . . . . . . . . . . . . . . . 16.5 cm (6.500 ±0.025 in) Board Width . . . . . . . . . . . . . . . . . . 11.4 cm (4.500 +0.005, -0.025 in) Board Thickness . . . . . . . . . . . . 1.575 mm (0.062 +0.007, -0.003 in) Board Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.5 g (10 oz) max. Component Height - Top - w/ battery, w/o 128 Kbyte Hybrid RAMs . . . . . . . . 12.7 mm (0.50 in) max.
Specifications .525 2.16 .12 .455 2.05 4.500 3.610 .40 6.500 All dimensions in inches. V20 C2 8087 .210 C1 zSBC 337 .230 Spacer Socket CPU BOARD Sockets for V20 Figure B–2. Board Dimensions With zSBC 337. B-8 .
Specifications CONNECTORS The ZT 8809A has nine connectors to interface to the I/O cables, the STD bus, the STD 32 bus, and application-specific devices. The board has four right angle frontplane connectors (J1 through J4) and two vertical mount frontplane connectors (J5 and J6). A vertical mount, two-pin socket connector (J7) is used for 8087 operation. The connectors are described below. Their locations are shown in Figures B-3 (page B-11) and B-4 (page B-12).
Specifications J3 and J4: Connectors J3 and J4 are latching 10-pin (dual 5-pin) male transition connectors with 0.1 inch lead spacing. J3 is used for the counter/timer inputs and outputs, and J4 is used for the frontplane interrupt inputs. The mating connector is a T&B Ansley #622-1001M or equivalent. The pin assignments are shown in Tables B-7 (page B-16) and B-8 (page B-17).
Specifications STD 32 STD 32 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 E41 E42 E43 E44 E45 E46 E47 E48 E49 E50 E51 E52 E53 E54 E55 E56 E57 E58 E59 E60 E61 E62 E63 E64 E65 E66 E67 E68 P01 P02 P03 P04 P05 P07 P06 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P4
Specifications TIMER COUNTER INTERRUPTS Pin 1 J3 J4 COM1 J2 J1 Pin 1 J6 LPT J7 P1 Figure B–4. ZT 8809A Connector Locations.
Specifications Table B-4 J1 Pin Assignments (RS-232-C). Signal TXD RXD RTS CTS DSR DTR RI DCD GND NC Pin Number DTE† DCE†† 3 5 7 9 11 14 12 10 1,13 2,4,6,8 5 3 9 7 14 11 12 10 1,13 2,4,6,8 Description Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Data Terminal Ready Ring Indicator Data Carrier Detect Ground No Connection † See Figure A-7 (page A-23) for configuration of jumpers W23-W28. †† See Figure A-8 (page A-24) for configuration of jumpers W23-W28 (factory default).
Specifications Table B-5 J2 Pin Assignments (RS-232-C). Signal TXD RXD RTS CTS DSR DTR RI DCD GND NC Pin Number DTE† DCE†† 3 5 7 9 11 14 12 10 1,13 2,4,6,8 5 3 9 7 14 11 12 10 1,13 2,4,6,8 Description Transmit Data Receive Data Request to Send Clear to Send Data Set Ready Data Terminal Ready Ring Indicator Data Carrier Detect Ground No Connection † See Figure A-4 (page A-19) for jumper assignments/configuration. †† See Figure A-3 (page A-18) for jumper assignments/configuration (factory default).
Specifications Table B-6 J2 Pin Assignments (RS-422/485).
Specifications Table B-7 J3 Pin Assignments.
Specifications Table B-8 J4 Pin Assignments. Signal Pin Number FP1 FP3 FP5 FP6 FP7 2 4 6 8 10 Description Frontplane Interrupt Level 1 Frontplane Interrupt Level 3 Frontplane Interrupt Level 5 Frontplane Interrupt Level 6 Frontplane Interrupt Level 7 Table B-9 J5 Pin Assignments.
Specifications Table B-10 J6 Pin Assignments.
Specifications Table B-11 J7 Pin Assignments.
Specifications CABLES 40"+1" TB ANSLEY 622-1430 FEMALE .025" SQ. 14 PIN CONNECTOR POLARIZED TB ANSLEY 622-25S FEMALE 25 PIN "D" CONNECTOR TB ANSLEY 171-25 25 CONDUCTOR 28 GA. STRANDED FLAT CABLE TRIM 15-25 AT CONNECTOR BLUE WIRE PIN 1 PIN 1 P1 J1 P1 J1 1 1 8 17 2 3 4 14 2 15 3 16 4 9 10 11 12 13 14 5 18 6 19 5 6 7 7 20 Figure B–5. ZT 90014 Cable Drawing.
Specifications 40"+1" TB ANSLEY 622-1430 FEMALE .025" SQ. 14 PIN CONNECTOR POLARIZED TB ANSLEY 622-25P MALE 25 PIN "D" CONNECTOR TB ANSLEY 171-25 25 CONDUCTOR 28 GA. STRANDED FLAT CABLE TRIM 15-25 AT CONNECTOR P1 J1 PIN 1 BLUE WIRE PIN 1 P1 J1 P1 J1 17 5 18 6 19 7 20 1 1 8 2 3 4 14 2 15 3 16 4 9 10 11 12 13 14 5 6 7 Figure B–6. ZT 90027 Cable Drawing.
Specifications 36+1/2" Pin 1 Pin 1 Stripe CON-00052 and CON-00098 Circuit Assembly CA-25DSS-3 and Tex-Techs FCH 25A, respectively (screws, if any, removed from backshell) Female 25 Pin D-Type Connector with solder pot leads and metalized backshell CON-00090 TB Ansley 622-2041 TB Ansley 171-20 .025" square 20 pin polarized connector with strain relief 20 conductor 28 guage stranded flat cable Hex Standoffs 4-40 (2 places) Pin Assignment Chart Wire No.
Specifications TIMING The ZT 8809A timing parameters shown in the following pages are based on the STD bus CLOCK* signal. The CLOCK* signal has rise and fall times of less than 10 ns as illustrated below. tW1 tW2 SYMBOL PARAMETER tW3 8808A 8809A 88CT08A 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tW1 tW2 tW3 8088 CLOCK* period 8088 CLOCK* high width 8088 CLOCK* low width 200 118 69 125 69 44 200 118 69 125 69 44 Figure B–8. ZT 8809A CLOCK* Timing.
Specifications T1 tW1 tW7 tW2 tW8 T2 T3 /TW T4 tW3 tW9 CLOCK* tD2 tD1 tW4 MCSYNC* tD3 A0-A15 IOEXP MEMEX tH4 VALID tH1 tD4 STATUS 0* VALID STATUS 1* tH2 tD5 IORQ* VALID tD6 tH3 MEMRQ* SYMBOL VALID PARAMETER 8808A 8809A 88CT08A 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD1 tD2 tD3 tD4 tD5 tD6 tH1 tH2 tH3 tH4 tW4 Delay from CLOCK * to MCSYNC* low Delay from CLOCK* to MCSYNC* high Delay from CLOCK* to Address 0-15, MEMEX, IOEXP Delay from CLOCK* to STATUS Delay from CLOCK* to IORQ* Delay
Specifications T1 T2 T3 /TW T4 CLOCK* tD2 tD1 tW4 MCSYNC* tD3 tD7 tH4 A0-A15 IOEXP MEMEX tS1 tD9 tD8 tH8 DATA tD10 tH9 tS2 A16-A19 VALID VALID tD12 tD11 RD* tW5 SYMBOL PARAMETER ZT 8808A ZT 8809A ZT 88CT08A ZT 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD1 tD2 tD3 tD7 tD8 tD9 tD10 tD11 tD12 tH4 tH8 tH9 tS1 tS2 tW4 tW5 Delay from CLOCK * to MCSYNC* low Delay from CLOCK* to MCSYNC* high Delay from CLOCK* to Address 0-15 Delay from Address 0-15, MEMEX, IOEXP to data valid Delay from Addre
Specifications T1 T2 T3 /TW T4 CLOCK* tD2 tD1 tW4 MCSYNC* tD3 tH4 A0-A15 IOEXP MEMEX VALID tH8 tS1 tD9 tD13 A16-A19 VALID DATA tH10 VALID tD14 tW6 tD15 WR* tH11 SYMBOL PARAMETER ZT 8808A ZT 8809A ZT 88CT08A ZT 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD1 tD2 tD3 tD9 tD13 tD14 tD15 tH4 tH8 tH10 tH11 tS1 tW4 tW6 Delay from CLOCK * to MCSYNC* low Delay from CLOCK* to MCSYNC* high Delay from CLOCK* to Address 0-15, MEMEX, IOEXP Delay from CLOCK* to Address 16-19 Delay from CLOCK* to Data
Specifications T1 T2 T3 TW T4 CLOCK* tD2 tD1 tW4 MCSYNC* tH14 tS4 tH14 WAITRQ* (2) tS5 tS4 tH14 WAITRQ* (2) tS7 SYMBOL tH14 tS5 A0-A19 PARAMETER ZT 8808A ZT8809A ZT 88CT08A ZT 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD1 tD2 tH14 tS4 tS5 tS7 tW4 Delay from CLOCK* to MCSYNC* low Delay from CLOCK* to MCSYNC high WAITRQ* hold after CLOCK* WAITRQ* low setup to CLOCK* WAITRQ* high setup to CLOCK* Address 0-19 setup to WAITRQ* (end of T 2 ) MCSYNC* pulse width 1 6 0 45 45 249 85 69 22 1 6 0
Specifications CLOCK* (1) BUSRQ* tD22 tD21 BUSAK* tD23 DBUS D0-D7 tD24 DMA USE CPU USE CPU USE tD25 A0-A15 tD26 DMA USE CPU USE CPU USE tD27 (2) CONTROL SYMBOL tD28 DMA USE CPU USE PARAMETER CPU USE ZT 8808A ZT 8809A ZT 88CT08A ZT 88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD21 tD22 tH23 tD24 tD25 tD26 tD27 tD28 Delay from CLOCK* to BUSAK* low Delay from CLOCK* to BUSAK* high Delay from BUSAK* to Data Bus 3-State Delay from BUSAK* to Data Bus driven Delay from BUSAK* to Address Bus 3-State
Specifications T1 T2 T3 T4 T1 T2 T3 T4 CLOCK* MCSYNC* tD19 tD18 tD18 tD19 INTAK* tD9 (2) DATA BUS tD9 tD20 tS3 tD20 D0-D3 UNDETERMINED D0-D3 UNDETERMINED tH13 POINTER IN tD36 tH17 (3) A0-A15 VALID CASCADE # tD37 tD39 FLOAT (3) A0-A15 tD38 tH18 (4) A0-A15 SYMBOL VALID CASCADE # PARAMETER ZT 8808A ZT 8809A ZT 88CT08A ZT88CT09A MIN MAX MIN MAX MIN MAX MIN MAX tD9 tD18 tD19 tD20 tD36 tD37 tD38 tD39 tH13 tH17 tH18 tS3 Delay from CLOCK* to Address 16-19 Delay from CLOCK * to I
Appendix C CUSTOMER SUPPORT Contents Page OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Powering Up STD ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Powering Up STD DOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 ZT 8808A/8809A REVISION HISTORY . . . . . . .
Customer Support TROUBLESHOOTING Powering Up STD ROM If you are having difficulty powering up under STD ROM, be sure the EPROM, RAM, jumpers, and cable are correctly configured. Check that the ZT 8809A is installed securely in the STD bus card cage. Be sure you have attached the D-type connector end of the cable to the appropriate IBM PC or compatible, or to a terminal. • C-2 Follow these steps to power on the system with a PC or compatible. 1. Turn on the PC and wait for the DOS prompt. 2.
Customer Support • Some things to check if the system is not working: 1. Two ZT 8809A frontplane connectors accept the ZT 90014 serial cable. STD ROM works only in serial port 1 at J1. 2. If a PC is used that has more than one 25-pin male connector, be sure the serial cable is plugged into COM1. 3. Check to see the EPROM and RAM chips are installed in the proper sockets. EPROM should be installed in socket 5D1. RAM should be installed in socket 7D1. 4.
Customer Support Powering Up STD DOS Be sure the ZT 8809A is seated securely into the card cage and the power switch is off. Plug the card cage into a 120 VAC source. Refer to the following instructions appropriate for your configuration (PC-Assisted with a host computer, PC-Assisted with a terminal or video board, or Automation Engine). • PC-Assisted with a host computer - An IBM PC or compatible is used to communicate with the ZT 8809A STD DOS system. 1.
Customer Support • PC-Assisted with a terminal or video board - The PCAssisted system can also communicate with a terminal via COM2 or through a Ziatech EGA video board with keyboard support. 1. If you are using a terminal for communication with the ZT 8809A STD DOS system, connect the system’s serial cable from the proper ZT 8809A serial port to the terminal. 2. If you are using a video board: 3. a) The ZT 8844 EGA video board is shipped configured for a monochrome monitor.
Customer Support • The Automation Engine is available for OEM system designers or high volume users of the ZT 8809A STD DOS system. The ZT 8809A is shipped with a license for DOS, and it is used for systems with completed application software. It is assumed here that the user is familiar with the ZT 8809A STD DOS system. • Some things to look for if the system didn’t boot: 1. C-6 The LED near the extractor should have lit (this is set by DOS).
Customer Support 2. 3. If the system completes the RAM test, but does not continue, check the following: a) Check the assignment of jumpers W57-W59, as explained in Appendix A. b) Be sure W12 (located next to the battery) is installed to allow DOS access to the RAM drive that contains the configuration variables. c) Check the placement of the STD DOS EPROM in socket 5D1 and the 256 Kbytes of RAM in sockets 7D1 and 9D1.
Customer Support ZT 8808A/8809A REVISION HISTORY The ZT 8808A/8809A has undergone several revisions, some of which affect the functioning of the board from a user perspective. All of the functional changes for each revision are detailed in this section. Revision 0 - Original Release of Board, 12/17/91 The original artwork showed a revision level 0. The board contained wires to correct the item listed below. No boards were shipped without this correction: – Improper layout of W68.
Customer Support RELIABILITY Ziatech has taken extra care in the design of the ZT 8809A to ensure reliability. The four major ways in which reliability is achieved are: 1. The product was designed in top-down fashion, utilizing the latest in hardware and software design techniques, so that unwanted side effects and unclean interactions between parts of the system are eliminated. 2.
Customer Support WARRANTY Ziatech Hardware: Within two years of shipping date, Ziatech will repair or replace products which prove to be defective in materials and/or workmanship, provided they are promptly returned to Ziatech at customer’s expense and have not been repaired, altered, or damaged by non-Ziatech personnel. Service after warranty is available at a predesignated service charge. Batteries are not covered by this warranty. No other warranty is expressed or implied.
Customer Support TECHNICAL ASSISTANCE You can reach Ziatech’s Customer Support Service at one of the following numbers. Corporate Headquarters: (805) 541-0488 (805) 541-5088 (FAX) You can also use your modem to leave a message on the 24-hour Ziatech Bulletin Board Service (BBS) by calling (805) 541-8218. The BBS will provide you with current Ziatech product revision and upgrade information.
Customer Support RETURNING FOR SERVICE Before returning any of Ziatech’s products, you must obtain a Returned Material Authorization (RMA) number by calling (805) 541-0488. We will need the following information to expedite the return of your board: 1. Your company name and address for invoice 2. Shipping address and phone number 3. Product I.D. number 4.
INDEX -Aaccess times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 AC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 calibration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 AC power-fail . . . . . . . . .
Index ZT 8809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 board dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 Borland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7, C-2 break for emulation (BRKEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 break interrupt (BI) indicator . . . . . . . . . . .
Index electrical/environmental differences . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 functional differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29, 13-2 halt with restart via interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 logic family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 CNTRL* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index simple read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 creating EPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 -Ddata communication equipment (DCE) . . . .
Index End-of-Interrupt (EOI) commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 automatic EOI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 nonspecific EOI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 specific EOI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 when to use automatic EOI mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index -IIBM-LPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 IBM PC compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1, 1-9 IBM PC performance compared to ZT 8809A . . . . . . . . . . . . . . . . . . . . 3-3 index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 initialization and operation registers . . . . . . . . . . . . . . . . .
Index interrupt on terminal count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 interrupt request register (IRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 interrupt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11, 3-8 8087 . . . . . . . . . . . . . . . . . . . . . . . . .
Index LOCATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 loop counter (LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 -MMEMEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 memory access times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 addressing . . . . . .
Index -Ooperation control words (OCWs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 operation of the interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 automatic rotating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 edge-triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 fully nested mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index printer interface (see Centronics printer interface) . . . . . . . . . . . . . . . . 9-1 priority resolver (PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 processor performance compared to IBM PC . . . . . . . . . . . . . . . . . . . . . 3-3 program counter and prefetch pointer (PC and PFP) . . . . . . . . . . . . . 6-10 program counter (PC) [IP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index summary (16C452) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 request to send (RTS*) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15, 8-31 RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 RESET . . . . . . . . . . . . . . . . . . . . . . . .
Index serial data outputs (SOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 serial registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 divisor latch access bit (DLAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 internal ID register (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . .
Index STD DOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7, 3-4, 3-8, 5-3 cable requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 configuring the ZT 8809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 default jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14, 5-5 default memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index zero bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 timekeeper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-23 trailing edge of ring indicator (TERI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 transformer calibration sequence . . . . . . . . . . . . .
Index what’s in the box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 -ZzSBC 337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12, 7-3 installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 ZT 90020 AC converter . . . .
