Specifications

High Speed Data Ports 9-5
RATE
The Rate setting allows you to select the bandwidth for all time slots assigned to this port. The
available options are 56k or 64k. This selection is multiplied by the number of time slots
assigned to the port, to define the overall port speed. For example, if you choose 64k as the
port Rate and assign four time slots to that port, the overall port speed is 256 kbps.
Tx CLOCK
The Transmit Clock (Tx CLOCK) setting identifies the clock source for the SD (send data)
signal from the external CPE. The int (internal) setting requires an external DTE to
synchronize its transmitted data with the clock on the SCT leads. The ext (extended) setting
requires the DTE to synchronize its transmitted data with the clock on the SCTE leads.
Use ext with a long cable run to ensure the data and clock are in-phase when they arrive at the
system. The DTE must loop back the clock on the SCT leads to the SCTE leads.
If ext is selected but the system does not detect an incoming clock on the SCTE leads, the HSU
Card automatically generates an internal clock. If this clock is not synchronized with the
incoming data, reset the CLOCK PLRTY option to synchronize the clock and data. The Tx
CLOCK PLRTY option settings are described in the next paragraphs.
Tx CLOCK PLRTY
The Transmit Clock Polarity (Tx CLOCK PLRTY) setting provides another way to
compensate for long cables in those cases where the DTE equipment does not provide SCTE.
When you choose inv (inverted mode), the relationship between the clock and data is altered
to compensate for long cable runs that the data signals must traverse between the card port and
CPE. When you choose norm (normal), the relationship between the clock and data is
unchanged. If you use inv, set the Tx CLK (Transmit Clock) option above to int (internal).
Rx CLOCK PLRTY
The Receive Clock Polarity (Rx CLOCK PLRTY) setting provides another way to
compensate for long cables in those cases where the DTE equipment does not provide SCTE.
When you choose inv (inverted mode), the relationship between the clock and data is altered
to compensate for long cable runs that the data signals must traverse between the card port and
CPE. When you choose norm (normal), the relationship between the clock and data is
unchanged. If you use inv, set the Tx CLK (Transmit Clock) option above to int (internal).