Service manual
DOUBLE-DENSITY
DISK
CONTROLLER
1
3
,.3
U6
CONTROL DECODER
AND
INVERTER
U6 is a programmable logic array,
designed
to
decode
address
and
read
and
write
conditions for
the
controller board. Using addresses
AO,
Al,
and
A2
it
determines
whether
the
board is being addressed,
which
register is being addressed,
and
whether
the
signal is a read enable or
write
enable signal.
The
internal logic of U6,
and
most other ICs
on
the
board, is
shown
in
the
"Semiconduc-
tor Identification Chart." All
inputs
and
outputs
of
the
IC
are marked on
the
chart
as
they
are
on
the
Schematic.
U7
A ADDRESS CONTROL LATCH
The
address control latch
helps
call
up
the
registers
in
the
1797 - either
the
track
and
sector registers or
the
CiS
and
data registers,
depending
on
how
data bit 0 is
set
on
the
interface control latch.
U8A
RESET PULSE LATCH
The
reset
pulse
from
the
processor does
not
meet
the
minimum
reset
pulse
requirements
ofthe
1797. To correct this,
UBA
lengthens
the
reset
pulse
to
an
interval sufficientto meet
the
1797's specifications.
UBA
also
supplies
the
reset signal to U16,
part
of
the
phase
lock
loop circuitry. U16
then
resets
the
precompensation
clock generator, UIB.
U8B HEAD LOAD DELAY
UBB
is a monostable multivibrator
that
delays
the
controller's response to commands.
This allows
the
drive
head
to settle after
it
is selected.
U9
AND
Ul0
DISK CONTROLLER
CLOCK
U9 is a clock oscillator
that
runs
at 16 MHz.
The
output
of U9 is fed to
UI0.
UI0
divides
U9's
output
by 16,
producing
a 1 MHz clock signal
with
a 50%
duty
cycle.
Ull
INTERFACE CONTROL LATCH
The
Ull
is
an
octal type-D latch.
It
latches
the
high
speed
processor signals for
the
1797
disk controller (U12)
and
interface control latch
(Ull).
Some
commands,
such
as
MOTOR, go directly from
the
Ull
to
the
disk
drive interface ICs, U19, U20,
and
U21,
rather
than
through
the
1797.
U13
INPUT SIGNAL MULTIPLEXER
This
IC
multiplexes
the
control
and
data signalsfrom
the
two disk interfaces
into
the
disk
controller board.
The
multiplexer
switches
between
the
two
interface
line
groups,
depending
on
which
drive is selected
and
on
which
of
jumpers
J4, J5, J6,
or
J7
is set. The
multiplexerisolates
the
two
drive interfaces to preventtheir interfering
with
each other.