Service manual
3-
2
1L...
DOUBLE-DENSITY
DISK
CONTROLLER
CONTROL LINES (P2)
Please refer to
the
Schematic Diagram (fold-in)
while
you read this description.
All of
the
disk control
lines
from
the
processor are
input
to U6 via
plug
P2, except for
the
processor system clock line,
which
is
input
to U5A via
pin
13 of P2.
The
control
lines
consist ofaddress lines
AO,
Ai,
and
A2, read
line
RD,
write
line
WR,
I/O
DISK, I/O FLPY,
and
the
reset
line
RESET.lAddress
line
A2
is inverted
by
U5Bwhen
J1A
is jumpered. J1A is
jumpered
in
the
standard
operating mode, as is J2A.
Otherwise
A2
goes directly to U6.)
The
address
lines
access
the
1797 disk controller's (U12) registers.
The
read
and
write lines,
low
when
active, tell
the
controller
which
way
the
data buffer
direction control
should
be
set
and
whether
the
read or write lines to
the
disk
driver
electronics
should
be
used.
The
I/O DISK
and
I/O FLPY
lines
enable
the
controller board
and
tell
the
board
which
block of memory
in
the
processor is
used
for
disk
I/O.
The
I/O
DISK line is
used
in
the
standard
mode.
In
this
mode
the
I/O memory block base
address
is 170 octaLI/O FLPY,
when
connected
through
jumper
J2B, is
used
when
the
program-
mer
wishes to
designate
another
block of memory for
disk
I/O. The last control line,
RESET, initializes
the
controller.
Ut
DATA BUFFER
AND
U7B BUFFER DIRECTION CONTROL
The
data buffer is a bidirectional, eight-bit buffer whose direction is controlled by U7B,
the
buffer direction control.
U2, U3,
U4
INTERRUPT CONTROL
ICs U2
and
U4 are taken from
the
processor CPU board.
They
are
the
processor's
interrupt
channels.
They
are relocated onto
the
disk
controllerboard so
that
the
disk controller can
block all other
interrupts
to
the
processor exceptits own.
U3
screens
the
interrupt
signals
to
the
processor
under
Ull's
direction.
U3
turns
the
eight-bit
interrupt
to
the
processor
into three-bit
interrupt
signals.
The
three-bit
interrupt
becomes part of
an
eight-bit
data
instruction via U2.
U2
supplies
five other
hard
wired bits.
For more information about
U2
and
U4,
consult
your
processor's operation manual.
Us
OPEN COLLECTOR
NAND
GATES
There
are four gates
used
on
the
IC, called A,
B, C,
and
D.
The
gates invert the: processor
system clock for
use
by
the
1797,
interrupt
from
the
1797 to
the
processor,
and
address-
ing information from
the
processor to all parts of
the
disk controller board.
u