User Manual

MPA Project Document DOC #
XWING1 Users Guide
Copyright 2011 Motorola Solutions, Inc.
20110307-A 14 of 20
Confidential Material – Disclosure Strictly Prohibited.
 Accepts 19.2, 26, 38.4, 52-MHz reference clock Inputs for easy integration into cellular handsets
 IEEE Std 802.11d,e,h,i,k,r,s PICS compliant
 Supports Cisco Client eXtensions (CCX) standard
 Supports serial debug interface
 Supports Secure Digital Input/Output (SDIO) Serial Peripheral Interface (SPI) Host Interfaces
 Medium-Access Controller (MAC)
– Embedded ARM™ Central Processing Unit (CPU)
– Hardware-Based Encryption/Decryption Using 64-, 128-, and 256-Bit WEP, TKIP or AES Keys,
– Supports requirements for Wireless Fidelity (Wi-Fi) Protected Access (WPA and WPA2.0) and IEEE
Std 802.11i [Includes Hardware-Accelerated Advanced-Encryption Standard (AES)]
– Designed to Work With IEEE Std 802.1x for Virtual Private Network (VPN) Solutions
 Baseband Processor
– IEEE Std 802.11n single-stream data rates (MCS0-7) and SGI support
 2.4/5.0 GHz Radio
– Digital Radio Processor (DRP) implementation
– Internal LNA
– Supports : IEEE Std 802.11a, 802.11b, 802.11g, 802.11b/g and 802.11n
1.4.2. Bluetooth
Bluetooth 1.1, 1.2, 2.0+EDR and 2.1+EDR specification compliant (Lisbon release) - up to HCI level.
 BT Enhanced Data Rate (2 and 3 Mbps)
 Enhanced host interfaces (UART, btSPI)
 Very low power consumption
 On-chip Embedded radio
– Integrated 2.4 GHz RF transceiver
– All digital PLL transmitter with digitally controlled oscillator
– Near zero IF architecture
– On-chip TX/RX switch
– Support for Class-1.5 applications
 Embedded ARM Microprocessor System
– High rate four wire UART HCI (H4) and Three Wire UART HCI (H5)
– Automatic clock-detection mechanism
 Flexible PCM and I 2 S interfaces: full flexibility for data order, sampling and positioning
 Temperature detection and compensation mechanism ensures minimal variation in the RF
performance over the entire temperature range
 TI-proprietary low-power scan achieves paging and inquiry scans at 1/3 normal power.
 Digital Radio Processor (DRP) single-ended 50  I/O for easy RF interfacing
 Patch trap mechanism and reserved RAM enables easy bug fixes
 Advance Audio Interfaces and capabilities
– A2DP support
– A2DP internal loopback
– Wide-Band Speech support
– On board SBC encoder/decoder - offloads host for A2DP and WideBand speech processing