User's Manual

148603 Project Document
148603 Specification and Integration Guide
Copyright 2012 Motorola Solutions, Inc. 20110610-i 23 of 36
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5.4.2.3. SDIO Switching Characteristics
Over Recommended operating conditions
Parameters for maximum clock frequency
Table 11 – SDIO Timing
Parameter
Sym
Min.
Max.
Unit
Clock frequency, CLK Default Rate
fclock
0
26
MHz
Clock frequency, CLK High Rate
fclock
0
52
MHz
Low/high duty cycle
DC
40
60
%
Rise time, CLK
tTLH
1
3
ns
Fall time, CLK
tTHL
1
3
ns
Setup time, input valid before CLK
↑
tISU
2
ns
Hold time, input valid after CLK ↑
tIH
2
ns
Delay time, CLK ↓ to output valid
tODLY
2.5
14.8
ns
Capacitive load on outputs
Cl
15
pF
Table 12 - SDIO Timing