User`s manual

BL160064 s System Development
Prescaler
(PS)
)10
or
)30
Divide
Ratio
(
DR)
16
or
64
Baud Rate
Divider
)1
to
)64
Z180
Clock
External
Clock
The prescaler (PS) the divide ratio (DR) and the SS bits form a baud-rate
generator, as shown in Figure 4-14.
Figure 4-14. Baud-Rate Generator
DR (Divide Ratio)
This bit controls one stage of frequency division in the baud-rate generator.
If 1, then divide by 64. If 0, then divide by 16. This is the only control bit
that affects the external clock frequency.
PEO (Parity Even/Odd)
This bit affects parity: 0 ⇒ even parity, 1 ⇒ odd parity. It is effective only
if MOD1 is set in CNTLA (parity enabled).
CTS/PS (Clear to Send/Prescaler)
When read, this bit gives the state of external pin /CTS: 0⇒low,
1⇒high. When the /CTS pin is high, RDRF is inhibited so that incoming
receive characters are ignored. When written, this bit has an entirely
different function. If a 0 is written, the baud rate prescaler is set to divide
by 10. If a 1 is written, it is set to divide by 30.
MP (Multiprocessor Mode)
When this bit is set to 1, the multiprocessor mode is enabled. The multi-
processor bit (MPB) is included in transmitted data:
start bit,data bits,MPB,stop bits
The MPB is 1 when MPBT is 1 and 0 when MPBT is 0.
MPBT (Multiprocessor Bit Transmit)
This bit controls the multiprocessor bit (MPB). When the MPB is 1,
transmitted bytes will get the attention of other units listening only for
bytes with MPB set.