User`s manual

BL160062 s System Development
CNTLA0 (00H)
76543210
MPE RE TE /RTS0
MPBR/
EFR
MOD2 MOD1 MOD0
R / W R / W R / W R / W R / W R / W R / W R / W
CNTLA1 (01H)
76543210
MPE RE TE CKA1D
MPBR/
EFR
MOD2 MOD1 MOD0
R / W R / W R / W R / W R / W R / W R / W R / W
ASCI Control Register A
Control Register A affects various aspects of the asynchronous channel
operation.
MOD0MOD2 (Data Format Mode Bits)
MOD0 controls stop bits: 0 ⇒ 1 stop bit, 1 ⇒ 2 stop bits. If 2 stop bits
are expected, then 2 stop bits must be supplied.
MOD1 controls parity: 0 ⇒ parity disabled, 1 ⇒ parity enabled. (See
PEO in the ASCI Control Register B section for even/odd parity control.)
MOD2 controls data bits: 0 ⇒ 7 data bits, 1 ⇒ 8 data bits.
MPBR/EFR (Multiprocessor Bit Receive/Error Flag Reset)
Reads and writes on this bit are unrelated. Storing a byte when this bit is 0
clears all the error flags (OVRN, FE, PE). Reading this bit obtains the
value of the MPB bit for the last read operation when the multiprocessor
mode is enabled.
/RTS0 (Request to Send, Channel 0)
Store a 1 in this bit to set the RTS0 line from the Z180 high. This line is
further inverted by the output driver. This bit is essentially a 1-bit output
port without other side effects.
CKA1D (CKA1 Disable)
This bit controls the function assigned to the multiplexed pin (CKA1/
TEND0): 1 ⇒ TEND0 (a DMA function) and 0 ⇒ CKA1 (external clock
I/O for channel 1 serial port).
TE (Transmitter Enable)
This bit controls the transmitter: 1⇒transmitter enabled, 0⇒transmitter
disabled. When this bit is cleared, the processor aborts the operation in
progress, but does not disturb TDR or TDRE.